1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port header for AVR32 UC3.
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6 * - Compiler: GNU GCC for AVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support email: avr32@atmel.com
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13 *****************************************************************************/
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16 FreeRTOS.org V4.2.0 - Copyright (C) 2003-2007 Richard Barry.
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18 This file is part of the FreeRTOS.org distribution.
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20 FreeRTOS.org is free software; you can redistribute it and/or modify
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21 it under the terms of the GNU General Public License as published by
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22 the Free Software Foundation; either version 2 of the License, or
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23 (at your option) any later version.
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25 FreeRTOS.org is distributed in the hope that it will be useful,
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26 but WITHOUT ANY WARRANTY; without even the implied warranty of
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27 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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28 GNU General Public License for more details.
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30 You should have received a copy of the GNU General Public License
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31 along with FreeRTOS.org; if not, write to the Free Software
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32 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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34 A special exception to the GPL can be applied should you wish to distribute
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35 a combined work that includes FreeRTOS.org, without being obliged to provide
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36 the source code for any proprietary components. See the licensing section
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37 of http://www.FreeRTOS.org for full details of how and when the exception
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40 ***************************************************************************
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41 See http://www.FreeRTOS.org for documentation, latest information, license
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42 and contact details. Please ensure to read the configuration and relevant
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43 port sections of the online documentation.
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44 ***************************************************************************
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51 /*-----------------------------------------------------------
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52 * Port specific definitions.
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54 * The settings in this file configure FreeRTOS correctly for the
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55 * given hardware and compiler.
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57 * These settings should not be altered.
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58 *-----------------------------------------------------------
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60 #include <avr32/io.h>
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62 #include "compiler.h"
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65 /* Type definitions. */
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66 #define portCHAR char
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67 #define portFLOAT float
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68 #define portDOUBLE double
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69 #define portLONG long
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70 #define portSHORT short
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71 #define portSTACK_TYPE unsigned portLONG
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72 #define portBASE_TYPE portLONG
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74 #define TASK_DELAY_MS(x) ( (x) /portTICK_RATE_MS )
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75 #define TASK_DELAY_S(x) ( (x)*1000 /portTICK_RATE_MS )
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76 #define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_RATE_MS )
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78 #define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
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80 #if( configUSE_16_BIT_TICKS == 1 )
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81 typedef unsigned portSHORT portTickType;
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82 #define portMAX_DELAY ( portTickType ) 0xffff
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84 typedef unsigned portLONG portTickType;
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85 #define portMAX_DELAY ( portTickType ) 0xffffffff
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87 /*-----------------------------------------------------------*/
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89 /* Architecture specifics. */
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90 #define portSTACK_GROWTH ( -1 )
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91 #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
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92 #define portBYTE_ALIGNMENT 4
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93 #define portNOP() {__asm__ __volatile__ ("nop");}
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94 /*-----------------------------------------------------------*/
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97 /*-----------------------------------------------------------*/
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99 /* INTC-specific. */
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100 #define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
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101 #define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
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103 #define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
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104 #define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
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106 #define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
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107 #define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
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112 * Activated if and only if configDBG is nonzero.
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113 * Prints a formatted string to stdout.
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114 * The current source file name and line number are output with a colon before
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115 * the formatted string.
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116 * A carriage return and a linefeed are appended to the output.
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117 * stdout is redirected by Newlib to the USART configured by configDBG_USART.
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118 * The parameters are the same as for the standard printf function.
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119 * There is no return value.
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120 * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
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121 * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
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124 #define portDBG_TRACE(...) \
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126 fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
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127 printf(__VA_ARGS__);\
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128 fputs("\r\n", stdout);\
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131 #define portDBG_TRACE(...)
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135 /* Critical section management. */
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136 #define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
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137 #define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
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140 extern void vPortEnterCritical( void );
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141 extern void vPortExitCritical( void );
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143 #define portENTER_CRITICAL() vPortEnterCritical();
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144 #define portEXIT_CRITICAL() vPortExitCritical();
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147 /* Added as there is no such function in FreeRTOS. */
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148 extern void *pvPortRealloc( void *pv, size_t xSize );
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149 /*-----------------------------------------------------------*/
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152 /*=============================================================================================*/
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155 * Restore Context for cases other than INTi.
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157 #define portRESTORE_CONTEXT() \
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159 extern volatile unsigned portLONG ulCriticalNesting; \
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160 extern volatile void *volatile pxCurrentTCB; \
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162 __asm__ __volatile__ ( \
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163 /* Set SP to point to new stack */ \
\r
164 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
165 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
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166 "ld.w r0, r8[0] \n\t"\
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167 "ld.w sp, r0[0] \n\t"\
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169 /* Restore ulCriticalNesting variable */ \
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170 "ld.w r0, sp++ \n\t"\
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171 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
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172 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
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173 "st.w r8[0], r0 \n\t"\
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175 /* Restore R0..R7 */ \
\r
176 "ldm sp++, r0-r7 \n\t"\
\r
177 /* R0-R7 should not be used below this line */ \
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178 /* Skip PC and SR (will do it at the end) */ \
\r
179 "sub sp, -2*4 \n\t"\
\r
180 /* Restore R8..R12 and LR */ \
\r
181 "ldm sp++, r8-r12, lr \n\t"\
\r
183 "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \
\r
184 "mtsr %[SR], r0 \n\t"\
\r
186 "ld.w r0, sp[-9*4] \n\t"\
\r
188 "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
\r
190 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
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191 [pxCurrentTCB] "i" (&pxCurrentTCB), \
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192 [SR] "i" (AVR32_SR) \
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198 * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
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199 * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
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201 * Had to make different versions because registers saved on the system stack
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202 * are not the same between INT0..3 exceptions and the scall exception.
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205 // Task context stack layout:
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222 // ulCriticalNesting
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223 // (*) automatically done for INT0..INT3, but not for SCALL
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226 * The ISR used for the scheduler tick depends on whether the cooperative or
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227 * the preemptive scheduler is being used.
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229 #if configUSE_PREEMPTION == 0
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232 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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234 #define portSAVE_CONTEXT_OS_INT() \
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236 /* Save R0..R7 */ \
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237 __asm__ __volatile__ ("stm --sp, r0-r7"); \
\r
239 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
240 /* there is also no context save. */ \
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244 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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246 #define portRESTORE_CONTEXT_OS_INT() \
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248 __asm__ __volatile__ ( \
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249 /* Restore R0..R7 */ \
\r
250 "ldm sp++, r0-r7\n\t" \
\r
252 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
253 /* there is also no context restore. */ \
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261 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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263 #define portSAVE_CONTEXT_OS_INT() \
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265 extern volatile unsigned portLONG ulCriticalNesting; \
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266 extern volatile void *volatile pxCurrentTCB; \
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268 /* When we come here */ \
\r
269 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
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271 __asm__ __volatile__ ( \
\r
272 /* Save R0..R7 */ \
\r
273 "stm --sp, r0-r7 \n\t"\
\r
275 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
276 "mov r8, LO(%[ulCriticalNesting])\n\t" \
\r
277 "orh r8, HI(%[ulCriticalNesting])\n\t" \
\r
278 "ld.w r0, r8[0] \n\t"\
\r
279 "st.w --sp, r0 \n\t"\
\r
281 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
282 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
283 /* level and allow other lower interrupt level to occur). */ \
\r
284 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
285 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
286 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
287 /* will just be restoring the interrupt handler, no way!!! */ \
\r
288 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
289 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
\r
290 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
\r
291 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
\r
292 "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
\r
294 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
295 /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
\r
296 /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
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297 /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
\r
298 /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
\r
299 "mov r8, LO(%[pxCurrentTCB])\n\t" \
\r
300 "orh r8, HI(%[pxCurrentTCB])\n\t" \
\r
301 "ld.w r0, r8[0]\n\t" \
\r
302 "st.w r0[0], sp\n" \
\r
304 "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \
\r
306 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
307 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
308 [LINE] "i" (__LINE__) \
\r
313 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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315 #define portRESTORE_CONTEXT_OS_INT() \
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317 extern volatile unsigned portLONG ulCriticalNesting; \
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318 extern volatile void *volatile pxCurrentTCB; \
\r
320 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
321 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
322 /* level and allow other lower interrupt level to occur). */ \
\r
323 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
324 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
325 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
326 /* will just be restoring the interrupt handler, no way!!! */ \
\r
327 __asm__ __volatile__ ( \
\r
328 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
\r
329 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
\r
330 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
\r
331 "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \
\r
333 : [LINE] "i" (__LINE__) \
\r
337 /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
\r
338 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
\r
339 portENTER_CRITICAL(); \
\r
340 vTaskSwitchContext(); \
\r
341 portEXIT_CRITICAL(); \
\r
343 /* Restore all registers */ \
\r
345 __asm__ __volatile__ ( \
\r
346 /* Set SP to point to new stack */ \
\r
347 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
348 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
349 "ld.w r0, r8[0] \n\t"\
\r
350 "ld.w sp, r0[0] \n"\
\r
352 "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
\r
354 /* Restore ulCriticalNesting variable */ \
\r
355 "ld.w r0, sp++ \n\t" \
\r
356 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
357 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
358 "st.w r8[0], r0 \n\t"\
\r
360 /* Restore R0..R7 */ \
\r
361 "ldm sp++, r0-r7 \n\t"\
\r
363 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
366 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
367 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
368 [LINE] "i" (__LINE__) \
\r
376 * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
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378 * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
\r
381 #define portSAVE_CONTEXT_SCALL() \
\r
383 extern volatile unsigned portLONG ulCriticalNesting; \
\r
384 extern volatile void *volatile pxCurrentTCB; \
\r
386 /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
\r
387 /* If SR[M2:M0] == 001 */ \
\r
388 /* PC and SR are on the stack. */ \
\r
389 /* Else (other modes) */ \
\r
390 /* Nothing on the stack. */ \
\r
392 /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
\r
393 /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
\r
394 /* in an interrupt|exception handler. */ \
\r
396 __asm__ __volatile__ ( \
\r
397 /* in order to save R0-R7 */ \
\r
398 "sub sp, 6*4 \n\t"\
\r
399 /* Save R0..R7 */ \
\r
400 "stm --sp, r0-r7 \n\t"\
\r
402 /* in order to save R8-R12 and LR */ \
\r
403 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
404 "sub r7, sp,-16*4 \n\t"\
\r
405 /* Copy PC and SR in other places in the stack. */ \
\r
406 "ld.w r0, r7[-2*4] \n\t" /* Read SR */\
\r
407 "st.w r7[-8*4], r0 \n\t" /* Copy SR */\
\r
408 "ld.w r0, r7[-1*4] \n\t" /* Read PC */\
\r
409 "st.w r7[-7*4], r0 \n\t" /* Copy PC */\
\r
411 /* Save R8..R12 and LR on the stack. */ \
\r
412 "stm --r7, r8-r12, lr \n\t"\
\r
414 /* Arriving here we have the following stack organizations: */ \
\r
415 /* R8..R12, LR, PC, SR, R0..R7. */ \
\r
417 /* Now we can finalize the save. */ \
\r
419 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
420 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
421 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
422 "ld.w r0, r8[0] \n\t"\
\r
425 : [ulCriticalNesting] "i" (&ulCriticalNesting) \
\r
428 /* Disable the its which may cause a context switch (i.e. cause a change of */ \
\r
429 /* pxCurrentTCB). */ \
\r
430 /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
\r
431 /* critical section because it is a global structure. */ \
\r
432 portENTER_CRITICAL(); \
\r
434 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
435 __asm__ __volatile__ ( \
\r
436 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
437 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
438 "ld.w r0, r8[0] \n\t"\
\r
441 : [pxCurrentTCB] "i" (&pxCurrentTCB) \
\r
446 * portRESTORE_CONTEXT() for SupervisorCALL exception.
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448 #define portRESTORE_CONTEXT_SCALL() \
\r
450 extern volatile unsigned portLONG ulCriticalNesting; \
\r
451 extern volatile void *volatile pxCurrentTCB; \
\r
453 /* Restore all registers */ \
\r
455 /* Set SP to point to new stack */ \
\r
456 __asm__ __volatile__ ( \
\r
457 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
458 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
459 "ld.w r0, r8[0] \n\t"\
\r
462 : [pxCurrentTCB] "i" (&pxCurrentTCB) \
\r
465 /* Leave pxCurrentTCB variable access critical section */ \
\r
466 portEXIT_CRITICAL(); \
\r
468 __asm__ __volatile__ ( \
\r
469 /* Restore ulCriticalNesting variable */ \
\r
470 "ld.w r0, sp++ \n\t"\
\r
471 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
472 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
473 "st.w r8[0], r0 \n\t"\
\r
475 /* skip PC and SR */ \
\r
476 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
477 "sub r7, sp, -10*4 \n\t"\
\r
478 /* Restore r8-r12 and LR */ \
\r
479 "ldm r7++, r8-r12, lr \n\t"\
\r
481 /* RETS will take care of the extra PC and SR restore. */ \
\r
482 /* So, we have to prepare the stack for this. */ \
\r
483 "ld.w r0, r7[-8*4] \n\t" /* Read SR */\
\r
484 "st.w r7[-2*4], r0 \n\t" /* Copy SR */\
\r
485 "ld.w r0, r7[-7*4] \n\t" /* Read PC */\
\r
486 "st.w r7[-1*4], r0 \n\t" /* Copy PC */\
\r
488 /* Restore R0..R7 */ \
\r
489 "ldm sp++, r0-r7 \n\t"\
\r
491 "sub sp, -6*4 \n\t"\
\r
495 : [ulCriticalNesting] "i" (&ulCriticalNesting) \
\r
501 * The ISR used depends on whether the cooperative or
\r
502 * the preemptive scheduler is being used.
\r
504 #if configUSE_PREEMPTION == 0
\r
507 * ISR entry and exit macros. These are only required if a task switch
\r
508 * is required from the ISR.
\r
510 #define portENTER_SWITCHING_ISR() \
\r
512 /* Save R0..R7 */ \
\r
513 __asm__ __volatile__ ("stm --sp, r0-r7"); \
\r
515 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
516 /* there is also no context save. */ \
\r
520 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
522 #define portEXIT_SWITCHING_ISR() \
\r
524 __asm__ __volatile__ ( \
\r
525 /* Restore R0..R7 */ \
\r
526 "ldm sp++, r0-r7 \n\t"\
\r
528 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
529 /* there is also no context restore. */ \
\r
537 * ISR entry and exit macros. These are only required if a task switch
\r
538 * is required from the ISR.
\r
540 #define portENTER_SWITCHING_ISR() \
\r
542 extern volatile unsigned portLONG ulCriticalNesting; \
\r
543 extern volatile void *volatile pxCurrentTCB; \
\r
545 /* When we come here */ \
\r
546 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
\r
548 __asm__ __volatile__ ( \
\r
549 /* Save R0..R7 */ \
\r
550 "stm --sp, r0-r7 \n\t"\
\r
552 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
553 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
554 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
555 "ld.w r0, r8[0] \n\t"\
\r
556 "st.w --sp, r0 \n\t"\
\r
558 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
559 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
560 /* level and allow other lower interrupt level to occur). */ \
\r
561 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
562 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
563 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
564 /* will just be restoring the interrupt handler, no way!!! */ \
\r
565 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
566 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
567 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
568 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
569 "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
\r
571 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
572 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
573 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
574 "ld.w r0, r8[0] \n\t"\
\r
575 "st.w r0[0], sp \n"\
\r
577 "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
\r
579 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
580 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
581 [LINE] "i" (__LINE__) \
\r
586 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
588 #define portEXIT_SWITCHING_ISR() \
\r
590 extern volatile unsigned portLONG ulCriticalNesting; \
\r
591 extern volatile void *volatile pxCurrentTCB; \
\r
593 __asm__ __volatile__ ( \
\r
594 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
595 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
596 /* level and allow other lower interrupt level to occur). */ \
\r
597 /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
\r
598 /* did not previously save SP in its TCB. */ \
\r
599 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
600 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
601 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
602 "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\
\r
604 /* If a switch is required then we just need to call */ \
\r
605 /* vTaskSwitchContext() as the context has already been */ \
\r
607 "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
\r
608 "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
\r
610 : [LINE] "i" (__LINE__) \
\r
613 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
\r
614 portENTER_CRITICAL(); \
\r
615 vTaskSwitchContext(); \
\r
616 portEXIT_CRITICAL(); \
\r
618 __asm__ __volatile__ ( \
\r
619 "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\
\r
620 /* Restore the context of which ever task is now the highest */ \
\r
621 /* priority that is ready to run. */ \
\r
623 /* Restore all registers */ \
\r
625 /* Set SP to point to new stack */ \
\r
626 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
627 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
628 "ld.w r0, r8[0] \n\t"\
\r
629 "ld.w sp, r0[0] \n"\
\r
631 "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
\r
633 /* Restore ulCriticalNesting variable */ \
\r
634 "ld.w r0, sp++ \n\t"\
\r
635 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
636 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
637 "st.w r8[0], r0 \n\t"\
\r
639 /* Restore R0..R7 */ \
\r
640 "ldm sp++, r0-r7 \n\t"\
\r
642 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
645 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
646 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
647 [LINE] "i" (__LINE__) \
\r
654 #define portYIELD() {__asm__ __volatile__ ("scall");}
\r
656 /* Task function macros as described on the FreeRTOS.org WEB site. */
\r
657 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
658 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
661 #endif /* PORTMACRO_H */
\r
projects / freertos / blob