2 FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 See http://www.FreeRTOS.org for documentation, latest information, license
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28 and contact details. Please ensure to read the configuration and relevant
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29 port sections of the online documentation.
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31 Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
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32 with commercial development and support options.
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33 ***************************************************************************
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36 /*-----------------------------------------------------------
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37 * Implementation of functions defined in portable.h for the MicroBlaze port.
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38 *----------------------------------------------------------*/
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41 /* Scheduler includes. */
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42 #include "FreeRTOS.h"
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45 /* Standard includes. */
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48 /* Hardware includes. */
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50 #include <xintc_i.h>
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51 #include <xtmrctr.h>
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53 /* Tasks are started with interrupts enabled. */
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54 #define portINITIAL_MSR_STATE ( ( portSTACK_TYPE ) 0x02 )
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56 /* Tasks are started with a critical section nesting of 0 - however prior
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57 to the scheduler being commenced we don't want the critical nesting level
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58 to reach zero, so it is initialised to a high value. */
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59 #define portINITIAL_NESTING_VALUE ( 0xff )
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61 /* Our hardware setup only uses one counter. */
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62 #define portCOUNTER_0 0
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64 /* The stack used by the ISR is filled with a known value to assist in
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66 #define portISR_STACK_FILL_VALUE 0x55555555
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68 /* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
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69 maintains it's own count, so this variable is saved as part of the task
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71 volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE;
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73 /* To limit the amount of stack required by each task, this port uses a
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74 separate stack for interrupts. */
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75 unsigned portLONG *pulISRStack;
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77 /*-----------------------------------------------------------*/
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80 * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but
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81 * could have alternatively used the watchdog timer or timer 1.
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83 static void prvSetupTimerInterrupt( void );
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84 /*-----------------------------------------------------------*/
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87 * Initialise the stack of a task to look exactly as if a call to
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88 * portSAVE_CONTEXT had been made.
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90 * See the header file portable.h.
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92 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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94 extern void *_SDA2_BASE_, *_SDA_BASE_;
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95 const unsigned portLONG ulR2 = ( unsigned portLONG ) &_SDA2_BASE_;
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96 const unsigned portLONG ulR13 = ( unsigned portLONG ) &_SDA_BASE_;
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98 /* Place a few bytes of known values on the bottom of the stack.
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99 This is essential for the Microblaze port and these lines must
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100 not be omitted. The parameter value will overwrite the
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101 0x22222222 value during the function prologue. */
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102 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;
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104 *pxTopOfStack = ( portSTACK_TYPE ) 0x22222222;
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106 *pxTopOfStack = ( portSTACK_TYPE ) 0x33333333;
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109 /* First stack an initial value for the critical section nesting. This
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110 is initialised to zero as tasks are started with interrupts enabled. */
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111 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0. */
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113 /* Place an initial value for all the general purpose registers. */
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115 *pxTopOfStack = ( portSTACK_TYPE ) ulR2; /* R2 - small data area. */
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117 *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3. */
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119 *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4. */
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121 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. */
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123 *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6. */
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125 *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7. */
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127 *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8. */
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129 *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9. */
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131 *pxTopOfStack = ( portSTACK_TYPE ) 0x0a; /* R10. */
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133 *pxTopOfStack = ( portSTACK_TYPE ) 0x0b; /* R11. */
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135 *pxTopOfStack = ( portSTACK_TYPE ) 0x0c; /* R12. */
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137 *pxTopOfStack = ( portSTACK_TYPE ) ulR13; /* R13 - small data read write area. */
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139 *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* R14. */
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141 *pxTopOfStack = ( portSTACK_TYPE ) 0x0f; /* R15. */
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143 *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R16. */
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145 *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R17. */
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147 *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R18. */
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149 *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R19. */
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151 *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R20. */
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153 *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R21. */
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155 *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R22. */
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157 *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R23. */
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159 *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R24. */
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161 *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R25. */
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163 *pxTopOfStack = ( portSTACK_TYPE ) 0x1a; /* R26. */
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165 *pxTopOfStack = ( portSTACK_TYPE ) 0x1b; /* R27. */
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167 *pxTopOfStack = ( portSTACK_TYPE ) 0x1c; /* R28. */
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169 *pxTopOfStack = ( portSTACK_TYPE ) 0x1d; /* R29. */
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171 *pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30. */
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174 /* The MSR is stacked between R30 and R31. */
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175 *pxTopOfStack = portINITIAL_MSR_STATE;
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178 *pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31. */
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181 /* Return a pointer to the top of the stack we have generated so this can
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182 be stored in the task control block for the task. */
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183 return pxTopOfStack;
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185 /*-----------------------------------------------------------*/
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187 portBASE_TYPE xPortStartScheduler( void )
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189 extern void ( __FreeRTOS_interrupt_Handler )( void );
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190 extern void ( vStartFirstTask )( void );
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193 /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */
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194 asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \
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195 "sw r6, r1, r0 \n\t" \
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196 "lhu r7, r1, r0 \n\t" \
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197 "shi r7, r0, 0x12 \n\t" \
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198 "shi r6, r0, 0x16 " );
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200 /* Setup the hardware to generate the tick. Interrupts are disabled when
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201 this function is called. */
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202 prvSetupTimerInterrupt();
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204 /* Allocate the stack to be used by the interrupt handler. */
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205 pulISRStack = ( unsigned portLONG * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
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207 /* Restore the context of the first task that is going to run. */
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208 if( pulISRStack != NULL )
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210 /* Fill the ISR stack with a known value to facilitate debugging. */
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211 memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
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212 pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
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214 /* Kick off the first task. */
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218 /* Should not get here as the tasks are now running! */
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221 /*-----------------------------------------------------------*/
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223 void vPortEndScheduler( void )
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225 /* Not implemented. */
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227 /*-----------------------------------------------------------*/
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230 * Manual context switch called by portYIELD or taskYIELD.
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232 void vPortYield( void )
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234 extern void VPortYieldASM( void );
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236 /* Perform the context switch in a critical section to assure it is
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237 not interrupted by the tick ISR. It is not a problem to do this as
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238 each task maintains it's own interrupt status. */
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239 portENTER_CRITICAL();
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240 /* Jump directly to the yield function to ensure there is no
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241 compiler generated prologue code. */
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242 asm volatile ( "bralid r14, VPortYieldASM \n\t" \
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243 "or r0, r0, r0 \n\t" );
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244 portEXIT_CRITICAL();
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246 /*-----------------------------------------------------------*/
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249 * Hardware initialisation to generate the RTOS tick.
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251 static void prvSetupTimerInterrupt( void )
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254 const unsigned portLONG ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
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255 unsigned portBASE_TYPE uxMask;
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257 /* The OPB timer1 is used to generate the tick. Use the provided library
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258 functions to enable the timer and set the tick frequency. */
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259 XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
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260 XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
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261 XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
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262 XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
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264 /* Set the timer interrupt enable bit while maintaining the other bit
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266 uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
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267 uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
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268 XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
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270 XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
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271 XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
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272 XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
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274 /*-----------------------------------------------------------*/
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277 * The interrupt handler placed in the interrupt vector when the scheduler is
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278 * started. The task context has already been saved when this is called.
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279 * This handler determines the interrupt source and calls the relevant
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280 * peripheral handler.
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282 void vTaskISRHandler( void )
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284 static unsigned portLONG ulPending;
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286 /* Which interrupts are pending? */
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287 ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
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289 if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
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291 static XIntc_VectorTableEntry *pxTablePtr;
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292 static XIntc_Config *pxConfig;
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293 static unsigned portLONG ulInterruptMask;
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295 ulInterruptMask = ( unsigned portLONG ) 1 << ulPending;
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297 /* Get the configuration data using the device ID */
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298 pxConfig = &XIntc_ConfigTable[ ( unsigned portLONG ) XPAR_INTC_SINGLE_DEVICE_ID ];
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300 pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
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301 if( pxConfig->AckBeforeService & ( ulInterruptMask ) )
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303 XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
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304 pxTablePtr->Handler( pxTablePtr->CallBackRef );
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308 pxTablePtr->Handler( pxTablePtr->CallBackRef );
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309 XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
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313 /*-----------------------------------------------------------*/
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316 * Handler for the timer interrupt.
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318 void vTickISR( void *pvBaseAddress )
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320 unsigned portLONG ulCSR;
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322 /* Increment the RTOS tick - this might cause a task to unblock. */
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323 vTaskIncrementTick();
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325 /* Clear the timer interrupt */
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326 ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);
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327 XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
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329 /* If we are using the preemptive scheduler then we also need to determine
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330 if this tick should cause a context switch. */
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331 #if configUSE_PREEMPTION == 1
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332 vTaskSwitchContext();
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335 /*-----------------------------------------------------------*/
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