git.sur5r.net Git - freertos/blob - Source/portable/GCC/STR75x/portISR.c

   1 /*\r
   2     FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.\r
   3         \r
   4 \r
   5     ***************************************************************************\r
   6      *                                                                       *\r
   7      *    FreeRTOS tutorial books are available in pdf and paperback.        *\r
   8      *    Complete, revised, and edited pdf reference manuals are also       *\r
   9      *    available.                                                         *\r
  10      *                                                                       *\r
  11      *    Purchasing FreeRTOS documentation will not only help you, by       *\r
  12      *    ensuring you get running as quickly as possible and with an        *\r
  13      *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
  14      *    the FreeRTOS project to continue with its mission of providing     *\r
  15      *    professional grade, cross platform, de facto standard solutions    *\r
  16      *    for microcontrollers - completely free of charge!                  *\r
  17      *                                                                       *\r
  18      *    >>> See http://www.FreeRTOS.org/Documentation for details. <<<     *\r
  19      *                                                                       *\r
  20      *    Thank you for using FreeRTOS, and thank you for your support!      *\r
  21      *                                                                       *\r
  22     ***************************************************************************\r
  23 \r
  24 \r
  25     This file is part of the FreeRTOS distribution.\r
  26 \r
  27     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  28     the terms of the GNU General Public License (version 2) as published by the\r
  29     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  30     >>>NOTE<<< The modification to the GPL is included to allow you to\r
  31     distribute a combined work that includes FreeRTOS without being obliged to\r
  32     provide the source code for proprietary components outside of the FreeRTOS\r
  33     kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
  34     WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
  35     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
  36     more details. You should have received a copy of the GNU General Public\r
  37     License and the FreeRTOS license exception along with FreeRTOS; if not it\r
  38     can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
  39     by writing to Richard Barry, contact details for whom are available on the\r
  40     FreeRTOS WEB site.\r
  41 \r
  42     1 tab == 4 spaces!\r
  43 \r
  44     http://www.FreeRTOS.org - Documentation, latest information, license and\r
  45     contact details.\r
  46 \r
  47     http://www.SafeRTOS.com - A version that is certified for use in safety\r
  48     critical systems.\r
  49 \r
  50     http://www.OpenRTOS.com - Commercial support, development, porting,\r
  51     licensing and training services.\r
  52 */\r
  53 \r
  54 \r
  55 /*-----------------------------------------------------------\r
  56  * Components that can be compiled to either ARM or THUMB mode are\r
  57  * contained in port.c  The ISR routines, which can only be compiled\r
  58  * to ARM mode, are contained in this file.\r
  59  *----------------------------------------------------------*/\r
  60 \r
  61 /*\r
  62 */\r
  63 \r
  64 /* Scheduler includes. */\r
  65 #include "FreeRTOS.h"\r
  66 #include "task.h"\r
  67 \r
  68 /* Constants required to handle critical sections. */\r
  69 #define portNO_CRITICAL_NESTING         ( ( unsigned long ) 0 )\r
  70 \r
  71 volatile unsigned long ulCriticalNesting = 9999UL;\r
  72 \r
  73 /*-----------------------------------------------------------*/\r
  74 \r
  75 /* \r
  76  * The scheduler can only be started from ARM mode, hence the inclusion of this\r
  77  * function here.\r
  78  */\r
  79 void vPortISRStartFirstTask( void );\r
  80 /*-----------------------------------------------------------*/\r
  81 \r
  82 void vPortISRStartFirstTask( void )\r
  83 {\r
  84         /* Simply start the scheduler.  This is included here as it can only be\r
  85         called from ARM mode. */\r
  86         asm volatile (                                                                                                          \\r
  87         "LDR            R0, =pxCurrentTCB                                                               \n\t"   \\r
  88         "LDR            R0, [R0]                                                                                \n\t"   \\r
  89         "LDR            LR, [R0]                                                                                \n\t"   \\r
  90                                                                                                                                                 \\r
  91         /* The critical nesting depth is the first item on the stack. */        \\r
  92         /* Load it into the ulCriticalNesting variable. */                                      \\r
  93         "LDR            R0, =ulCriticalNesting                                                  \n\t"   \\r
  94         "LDMFD  LR!, {R1}                                                                                       \n\t"   \\r
  95         "STR            R1, [R0]                                                                                \n\t"   \\r
  96                                                                                                                                                 \\r
  97         /* Get the SPSR from the stack. */                                                                      \\r
  98         "LDMFD  LR!, {R0}                                                                                       \n\t"   \\r
  99         "MSR            SPSR, R0                                                                                \n\t"   \\r
 100                                                                                                                                                 \\r
 101         /* Restore all system mode registers for the task. */                           \\r
 102         "LDMFD  LR, {R0-R14}^                                                                           \n\t"   \\r
 103         "NOP                                                                                                            \n\t"   \\r
 104                                                                                                                                                 \\r
 105         /* Restore the return address. */                                                                       \\r
 106         "LDR            LR, [LR, #+60]                                                                  \n\t"   \\r
 107                                                                                                                                                 \\r
 108         /* And return - correcting the offset in the LR to obtain the */        \\r
 109         /* correct address. */                                                                                          \\r
 110         "SUBS PC, LR, #4                                                                                        \n\t"   \\r
 111         );                                                                                                                                      \r
 112 }\r
 113 /*-----------------------------------------------------------*/\r
 114 \r
 115 void vPortTickISR( void )\r
 116 {\r
 117         /* Increment the RTOS tick count, then look for the highest priority \r
 118         task that is ready to run. */\r
 119         vTaskIncrementTick();\r
 120         \r
 121         #if configUSE_PREEMPTION == 1\r
 122                 vTaskSwitchContext();\r
 123         #endif\r
 124                         \r
 125         /* Ready for the next interrupt. */\r
 126         TB_ClearITPendingBit( TB_IT_Update );   \r
 127 }\r
 128 \r
 129 /*-----------------------------------------------------------*/\r
 130 \r
 131 /*\r
 132  * The interrupt management utilities can only be called from ARM mode.  When\r
 133  * THUMB_INTERWORK is defined the utilities are defined as functions here to\r
 134  * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then\r
 135  * the utilities are defined as macros in portmacro.h - as per other ports.\r
 136  */\r
 137 #ifdef THUMB_INTERWORK\r
 138 \r
 139         void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
 140         void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
 141 \r
 142         void vPortDisableInterruptsFromThumb( void )\r
 143         {\r
 144                 asm volatile ( \r
 145                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */\r
 146                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */\r
 147                         "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                                            */\r
 148                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */\r
 149                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
 150                         "BX             R14" );                                 /* Return back to thumb.                                        */\r
 151         }\r
 152                         \r
 153         void vPortEnableInterruptsFromThumb( void )\r
 154         {\r
 155                 asm volatile ( \r
 156                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */      \r
 157                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */      \r
 158                         "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                                                     */      \r
 159                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */      \r
 160                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
 161                         "BX             R14" );                                 /* Return back to thumb.                                        */\r
 162         }\r
 163 \r
 164 #endif /* THUMB_INTERWORK */\r
 165 /*-----------------------------------------------------------*/\r
 166 \r
 167 void vPortEnterCritical( void )\r
 168 {\r
 169         /* Disable interrupts as per portDISABLE_INTERRUPTS();                                                  */\r
 170         asm volatile ( \r
 171                 "STMDB  SP!, {R0}                       \n\t"   /* Push R0.                                                             */\r
 172                 "MRS    R0, CPSR                        \n\t"   /* Get CPSR.                                                    */\r
 173                 "ORR    R0, R0, #0xC0           \n\t"   /* Disable IRQ, FIQ.                                    */\r
 174                 "MSR    CPSR, R0                        \n\t"   /* Write back modified value.                   */\r
 175                 "LDMIA  SP!, {R0}" );                           /* Pop R0.                                                              */\r
 176 \r
 177         /* Now interrupts are disabled ulCriticalNesting can be accessed \r
 178         directly.  Increment ulCriticalNesting to keep a count of how many times\r
 179         portENTER_CRITICAL() has been called. */\r
 180         ulCriticalNesting++;\r
 181 }\r
 182 /*-----------------------------------------------------------*/\r
 183 \r
 184 void vPortExitCritical( void )\r
 185 {\r
 186         if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
 187         {\r
 188                 /* Decrement the nesting count as we are leaving a critical section. */\r
 189                 ulCriticalNesting--;\r
 190 \r
 191                 /* If the nesting level has reached zero then interrupts should be\r
 192                 re-enabled. */\r
 193                 if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
 194                 {\r
 195                         /* Enable interrupts as per portEXIT_CRITICAL().                                        */\r
 196                         asm volatile ( \r
 197                                 "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \r
 198                                 "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \r
 199                                 "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \r
 200                                 "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */      \r
 201                                 "LDMIA  SP!, {R0}" );                   /* Pop R0.                                              */\r
 202                 }\r
 203         }\r
 204 }\r
 205 \r
 206 \r
 207 \r
 208 \r
 209 \r