git.sur5r.net Git - freertos/blob - Source/portable/GCC/STR75x/portISR.c

   1 /*\r
   2         FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.\r
   3 \r
   4         This file is part of the FreeRTOS.org distribution.\r
   5 \r
   6         FreeRTOS.org is free software; you can redistribute it and/or modify\r
   7         it under the terms of the GNU General Public License as published by\r
   8         the Free Software Foundation; either version 2 of the License, or\r
   9         (at your option) any later version.\r
  10 \r
  11         FreeRTOS.org is distributed in the hope that it will be useful,\r
  12         but WITHOUT ANY WARRANTY; without even the implied warranty of\r
  13         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\r
  14         GNU General Public License for more details.\r
  15 \r
  16         You should have received a copy of the GNU General Public License\r
  17         along with FreeRTOS.org; if not, write to the Free Software\r
  18         Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA\r
  19 \r
  20         A special exception to the GPL can be applied should you wish to distribute\r
  21         a combined work that includes FreeRTOS.org, without being obliged to provide\r
  22         the source code for any proprietary components.  See the licensing section \r
  23         of http://www.FreeRTOS.org for full details of how and when the exception\r
  24         can be applied.\r
  25 \r
  26         ***************************************************************************\r
  27         See http://www.FreeRTOS.org for documentation, latest information, license \r
  28         and contact details.  Please ensure to read the configuration and relevant \r
  29         port sections of the online documentation.\r
  30 \r
  31         Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along\r
  32         with commercial development and support options.\r
  33         ***************************************************************************\r
  34 */\r
  35 \r
  36 \r
  37 /*-----------------------------------------------------------\r
  38  * Components that can be compiled to either ARM or THUMB mode are\r
  39  * contained in port.c  The ISR routines, which can only be compiled\r
  40  * to ARM mode, are contained in this file.\r
  41  *----------------------------------------------------------*/\r
  42 \r
  43 /*\r
  44 */\r
  45 \r
  46 /* Scheduler includes. */\r
  47 #include "FreeRTOS.h"\r
  48 #include "task.h"\r
  49 \r
  50 /* Constants required to handle critical sections. */\r
  51 #define portNO_CRITICAL_NESTING         ( ( unsigned portLONG ) 0 )\r
  52 \r
  53 volatile unsigned portLONG ulCriticalNesting = 9999UL;\r
  54 \r
  55 /*-----------------------------------------------------------*/\r
  56 \r
  57 /* \r
  58  * The scheduler can only be started from ARM mode, hence the inclusion of this\r
  59  * function here.\r
  60  */\r
  61 void vPortISRStartFirstTask( void );\r
  62 /*-----------------------------------------------------------*/\r
  63 \r
  64 void vPortISRStartFirstTask( void )\r
  65 {\r
  66         /* Simply start the scheduler.  This is included here as it can only be\r
  67         called from ARM mode. */\r
  68         asm volatile (                                                                                                          \\r
  69         "LDR            R0, =pxCurrentTCB                                                               \n\t"   \\r
  70         "LDR            R0, [R0]                                                                                \n\t"   \\r
  71         "LDR            LR, [R0]                                                                                \n\t"   \\r
  72                                                                                                                                                 \\r
  73         /* The critical nesting depth is the first item on the stack. */        \\r
  74         /* Load it into the ulCriticalNesting variable. */                                      \\r
  75         "LDR            R0, =ulCriticalNesting                                                  \n\t"   \\r
  76         "LDMFD  LR!, {R1}                                                                                       \n\t"   \\r
  77         "STR            R1, [R0]                                                                                \n\t"   \\r
  78                                                                                                                                                 \\r
  79         /* Get the SPSR from the stack. */                                                                      \\r
  80         "LDMFD  LR!, {R0}                                                                                       \n\t"   \\r
  81         "MSR            SPSR, R0                                                                                \n\t"   \\r
  82                                                                                                                                                 \\r
  83         /* Restore all system mode registers for the task. */                           \\r
  84         "LDMFD  LR, {R0-R14}^                                                                           \n\t"   \\r
  85         "NOP                                                                                                            \n\t"   \\r
  86                                                                                                                                                 \\r
  87         /* Restore the return address. */                                                                       \\r
  88         "LDR            LR, [LR, #+60]                                                                  \n\t"   \\r
  89                                                                                                                                                 \\r
  90         /* And return - correcting the offset in the LR to obtain the */        \\r
  91         /* correct address. */                                                                                          \\r
  92         "SUBS PC, LR, #4                                                                                        \n\t"   \\r
  93         );                                                                                                                                      \r
  94 }\r
  95 /*-----------------------------------------------------------*/\r
  96 \r
  97 void vPortTickISR( void )\r
  98 {\r
  99         /* Increment the RTOS tick count, then look for the highest priority \r
 100         task that is ready to run. */\r
 101         vTaskIncrementTick();\r
 102         \r
 103         #if configUSE_PREEMPTION == 1\r
 104                 vTaskSwitchContext();\r
 105         #endif\r
 106                         \r
 107         /* Ready for the next interrupt. */\r
 108         TB_ClearITPendingBit( TB_IT_Update );   \r
 109 }\r
 110 \r
 111 /*-----------------------------------------------------------*/\r
 112 \r
 113 /*\r
 114  * The interrupt management utilities can only be called from ARM mode.  When\r
 115  * THUMB_INTERWORK is defined the utilities are defined as functions here to\r
 116  * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then\r
 117  * the utilities are defined as macros in portmacro.h - as per other ports.\r
 118  */\r
 119 #ifdef THUMB_INTERWORK\r
 120 \r
 121         void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
 122         void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
 123 \r
 124         void vPortDisableInterruptsFromThumb( void )\r
 125         {\r
 126                 asm volatile ( \r
 127                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */\r
 128                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */\r
 129                         "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                                            */\r
 130                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */\r
 131                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
 132                         "BX             R14" );                                 /* Return back to thumb.                                        */\r
 133         }\r
 134                         \r
 135         void vPortEnableInterruptsFromThumb( void )\r
 136         {\r
 137                 asm volatile ( \r
 138                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */      \r
 139                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */      \r
 140                         "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                                                     */      \r
 141                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */      \r
 142                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
 143                         "BX             R14" );                                 /* Return back to thumb.                                        */\r
 144         }\r
 145 \r
 146 #endif /* THUMB_INTERWORK */\r
 147 /*-----------------------------------------------------------*/\r
 148 \r
 149 void vPortEnterCritical( void )\r
 150 {\r
 151         /* Disable interrupts as per portDISABLE_INTERRUPTS();                                                  */\r
 152         asm volatile ( \r
 153                 "STMDB  SP!, {R0}                       \n\t"   /* Push R0.                                                             */\r
 154                 "MRS    R0, CPSR                        \n\t"   /* Get CPSR.                                                    */\r
 155                 "ORR    R0, R0, #0xC0           \n\t"   /* Disable IRQ, FIQ.                                    */\r
 156                 "MSR    CPSR, R0                        \n\t"   /* Write back modified value.                   */\r
 157                 "LDMIA  SP!, {R0}" );                           /* Pop R0.                                                              */\r
 158 \r
 159         /* Now interrupts are disabled ulCriticalNesting can be accessed \r
 160         directly.  Increment ulCriticalNesting to keep a count of how many times\r
 161         portENTER_CRITICAL() has been called. */\r
 162         ulCriticalNesting++;\r
 163 }\r
 164 /*-----------------------------------------------------------*/\r
 165 \r
 166 void vPortExitCritical( void )\r
 167 {\r
 168         if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
 169         {\r
 170                 /* Decrement the nesting count as we are leaving a critical section. */\r
 171                 ulCriticalNesting--;\r
 172 \r
 173                 /* If the nesting level has reached zero then interrupts should be\r
 174                 re-enabled. */\r
 175                 if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
 176                 {\r
 177                         /* Enable interrupts as per portEXIT_CRITICAL().                                        */\r
 178                         asm volatile ( \r
 179                                 "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \r
 180                                 "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \r
 181                                 "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \r
 182                                 "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */      \r
 183                                 "LDMIA  SP!, {R0}" );                   /* Pop R0.                                              */\r
 184                 }\r
 185         }\r
 186 }\r
 187 \r
 188 \r
 189 \r
 190 \r
 191 \r