git.sur5r.net Git - freertos/blob - Source/portable/GCC/TriCore_1782/porttrap.c

   1 /*\r
   2     FreeRTOS V7.0.2 - Copyright (C) 2011 Real Time Engineers Ltd.\r
   3 \r
   4 \r
   5     ***************************************************************************\r
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  22     ***************************************************************************\r
  23 \r
  24 \r
  25     This file is part of the FreeRTOS distribution.\r
  26 \r
  27     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  28     the terms of the GNU General Public License (version 2) as published by the\r
  29     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
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  33     kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
  34     WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
  35     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
  36     more details. You should have received a copy of the GNU General Public\r
  37     License and the FreeRTOS license exception along with FreeRTOS; if not it\r
  38     can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
  39     by writing to Richard Barry, contact details for whom are available on the\r
  40     FreeRTOS WEB site.\r
  41 \r
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  44     http://www.FreeRTOS.org - Documentation, latest information, license and\r
  45     contact details.\r
  46 \r
  47     http://www.SafeRTOS.com - A version that is certified for use in safety\r
  48     critical systems.\r
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  50     http://www.OpenRTOS.com - Commercial support, development, porting,\r
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  52 */\r
  53 \r
  54 /* Kernel includes. */\r
  55 #include "FreeRTOS.h"\r
  56 \r
  57 /* Machine includes */\r
  58 #include <tc1782.h>\r
  59 #include <machine/intrinsics.h>\r
  60 #include <machine/cint.h>\r
  61 /*---------------------------------------------------------------------------*/\r
  62 \r
  63 /*\r
  64  * This reference is required by the Save/Restore Context Macros.\r
  65  */\r
  66 extern volatile unsigned portBASE_TYPE * pxCurrentTCB;\r
  67 /*-----------------------------------------------------------*/\r
  68 \r
  69 /*\r
  70  * This file contains base definitions for all of the possible traps in the system.\r
  71  * It is suggested to provide implementations for all of the traps but for\r
  72  * the time being they simply trigger a DEBUG instruction so that it is easy\r
  73  * to see what caused a particular trap.\r
  74  *\r
  75  * Trap Class 6, the SYSCALL, is used exclusively by the operating system.\r
  76  */\r
  77 \r
  78 /* The Trap Classes. */\r
  79 #define portMMU_TRAP                                                                            0\r
  80 #define portIPT_TRAP                                                                            1\r
  81 #define portIE_TRAP                                                                                     2\r
  82 #define portCM_TRAP                                                                                     3\r
  83 #define portSBP_TRAP                                                                            4\r
  84 #define portASSERT_TRAP                                                                         5\r
  85 #define portNMI_TRAP                                                                            7\r
  86 \r
  87 /* MMU Trap Identifications. */\r
  88 #define portTIN_MMU_VIRTUAL_ADDRESS_FILL                                        0\r
  89 #define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION                          1\r
  90 \r
  91 /* Internal Protection Trap Identifications. */\r
  92 #define portTIN_IPT_PRIVILIGED_INSTRUCTION                                      1\r
  93 #define portTIN_IPT_MEMORY_PROTECTION_READ                                      2\r
  94 #define portTIN_IPT_MEMORY_PROTECTION_WRITE                                     3\r
  95 #define portTIN_IPT_MEMORY_PROTECTION_EXECUTION                         4\r
  96 #define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS         5\r
  97 #define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS                      6\r
  98 #define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION  7\r
  99 \r
 100 /* Instruction Error Trap Identifications. */\r
 101 #define portTIN_IE_ILLEGAL_OPCODE                                                       1\r
 102 #define portTIN_IE_UNIMPLEMENTED_OPCODE                                         2\r
 103 #define portTIN_IE_INVALID_OPERAND                                                      3\r
 104 #define portTIN_IE_DATA_ADDRESS_ALIGNMENT                                       4\r
 105 #define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS                         5\r
 106 \r
 107 /* Context Management Trap Identifications. */\r
 108 #define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION                          1\r
 109 #define portTIN_CM_CALL_DEPTH_OVERFLOW                                          2\r
 110 #define portTIN_CM_CALL_DEPTH_UNDEFLOW                                          3\r
 111 #define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW                          4\r
 112 #define portTIN_CM_CALL_STACK_UNDERFLOW                                         5\r
 113 #define portTIN_CM_CONTEXT_TYPE                                                         6\r
 114 #define portTIN_CM_NESTING_ERROR                                                        7\r
 115 \r
 116 /* System Bus and Peripherals Trap Identifications. */\r
 117 #define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR                     1\r
 118 #define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR                       2\r
 119 #define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR                      3\r
 120 #define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR         4\r
 121 #define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR                      5\r
 122 #define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR                         6\r
 123 \r
 124 /* Assertion Trap Identifications. */\r
 125 #define portTIN_ASSERT_ARITHMETIC_OVERFLOW                                      1\r
 126 #define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW                       2\r
 127 \r
 128 /* Non-maskable Interrupt Trap Identifications. */\r
 129 #define portTIN_NMI_NON_MASKABLE_INTERRUPT                                      0\r
 130 /*---------------------------------------------------------------------------*/\r
 131 \r
 132 void vMMUTrap( int iTrapIdentification );\r
 133 void vInternalProtectionTrap( int iTrapIdentification );\r
 134 void vInstructionErrorTrap( int iTrapIdentification );\r
 135 void vContextManagementTrap( int iTrapIdentification );\r
 136 void vSystemBusAndPeripheralsTrap( int iTrapIdentification );\r
 137 void vAssertionTrap( int iTrapIdentification );\r
 138 void vNonMaskableInterruptTrap( int iTrapIdentification );\r
 139 /*---------------------------------------------------------------------------*/\r
 140 \r
 141 void vTrapInstallHandlers( void )\r
 142 {\r
 143         if ( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )\r
 144         {\r
 145                 _debug();\r
 146         }\r
 147         if ( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )\r
 148         {\r
 149                 _debug();\r
 150         }\r
 151         if ( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )\r
 152         {\r
 153                 _debug();\r
 154         }\r
 155         if ( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )\r
 156         {\r
 157                 _debug();\r
 158         }\r
 159         if ( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )\r
 160         {\r
 161                 _debug();\r
 162         }\r
 163         if ( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )\r
 164         {\r
 165                 _debug();\r
 166         }\r
 167 /*      Trap Handler 6 (Syscall) is installed in port.c as it is fundamental to\r
 168  *      the OS operation. These trap handlers is are place holders.\r
 169  *      if ( 0 != _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )\r
 170         {\r
 171                 _debug();\r
 172         }\r
 173 */\r
 174         if ( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )\r
 175         {\r
 176                 _debug();\r
 177         }\r
 178 }\r
 179 /*-----------------------------------------------------------*/\r
 180 \r
 181 void vMMUTrap( int iTrapIdentification )\r
 182 {\r
 183         switch ( iTrapIdentification )\r
 184         {\r
 185         case portTIN_MMU_VIRTUAL_ADDRESS_FILL:\r
 186         case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:\r
 187         default:\r
 188                 _debug();\r
 189                 break;\r
 190         }\r
 191 }\r
 192 /*---------------------------------------------------------------------------*/\r
 193 \r
 194 void vInternalProtectionTrap( int iTrapIdentification )\r
 195 {\r
 196         switch ( iTrapIdentification )\r
 197         {\r
 198         case portTIN_IPT_PRIVILIGED_INSTRUCTION:\r
 199                 /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */\r
 200         case portTIN_IPT_MEMORY_PROTECTION_READ:\r
 201                 /* Load word using invalid address. */\r
 202         case portTIN_IPT_MEMORY_PROTECTION_WRITE:\r
 203                 /* Store Word using invalid address. */\r
 204         case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:\r
 205                 /* PC jumped to an address outside of the valid range. */\r
 206         case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:\r
 207                 /* Access to a peripheral denied at current execution level. */\r
 208         case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:\r
 209                 /* NULL Pointer. */\r
 210         case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:\r
 211                 /* Tried to modify a global address pointer register. */\r
 212         default:\r
 213                 pxCurrentTCB[ 0 ] = _mfcr( $PCXI );\r
 214                 _debug();\r
 215                 break;\r
 216         }\r
 217 }\r
 218 /*---------------------------------------------------------------------------*/\r
 219 \r
 220 void vInstructionErrorTrap( int iTrapIdentification )\r
 221 {\r
 222         switch ( iTrapIdentification )\r
 223         {\r
 224         case portTIN_IE_ILLEGAL_OPCODE:\r
 225         case portTIN_IE_UNIMPLEMENTED_OPCODE:\r
 226         case portTIN_IE_INVALID_OPERAND:\r
 227         case portTIN_IE_DATA_ADDRESS_ALIGNMENT:\r
 228         case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:\r
 229         default:\r
 230                 _debug();\r
 231                 break;\r
 232         }\r
 233 }\r
 234 /*---------------------------------------------------------------------------*/\r
 235 \r
 236 void vContextManagementTrap( int iTrapIdentification )\r
 237 {\r
 238         switch ( iTrapIdentification )\r
 239         {\r
 240         case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:\r
 241         case portTIN_CM_CALL_DEPTH_OVERFLOW:\r
 242         case portTIN_CM_CALL_DEPTH_UNDEFLOW:\r
 243         case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:\r
 244         case portTIN_CM_CALL_STACK_UNDERFLOW:\r
 245         case portTIN_CM_CONTEXT_TYPE:\r
 246         case portTIN_CM_NESTING_ERROR:\r
 247         default:\r
 248                 _debug();\r
 249                 break;\r
 250         }\r
 251 }\r
 252 /*---------------------------------------------------------------------------*/\r
 253 \r
 254 void vSystemBusAndPeripheralsTrap( int iTrapIdentification )\r
 255 {\r
 256         switch ( iTrapIdentification )\r
 257         {\r
 258         case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:\r
 259         case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:\r
 260         case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:\r
 261         case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:\r
 262         case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:\r
 263         case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:\r
 264         default:\r
 265                 _debug();\r
 266                 break;\r
 267         }\r
 268 }\r
 269 /*---------------------------------------------------------------------------*/\r
 270 \r
 271 void vAssertionTrap( int iTrapIdentification )\r
 272 {\r
 273         switch ( iTrapIdentification )\r
 274         {\r
 275         case portTIN_ASSERT_ARITHMETIC_OVERFLOW:\r
 276         case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:\r
 277         default:\r
 278                 _debug();\r
 279                 break;\r
 280         }\r
 281 }\r
 282 /*---------------------------------------------------------------------------*/\r
 283 \r
 284 void vNonMaskableInterruptTrap( int iTrapIdentification )\r
 285 {\r
 286         switch ( iTrapIdentification )\r
 287         {\r
 288         case portTIN_NMI_NON_MASKABLE_INTERRUPT:\r
 289         default:\r
 290                 _debug();\r
 291                 break;\r
 292         }\r
 293 }\r
 294 /*---------------------------------------------------------------------------*/\r