1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port source for AVR32 UC3.
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6 * - Compiler: IAR EWAVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support and FAQ: http://support.atmel.no/
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13 *****************************************************************************/
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16 FreeRTOS.org V5.0.2 - Copyright (C) 2003-2008 Richard Barry.
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18 This file is part of the FreeRTOS.org distribution.
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20 FreeRTOS.org is free software; you can redistribute it and/or modify
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21 it under the terms of the GNU General Public License as published by
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22 the Free Software Foundation; either version 2 of the License, or
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23 (at your option) any later version.
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25 FreeRTOS.org is distributed in the hope that it will be useful,
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26 but WITHOUT ANY WARRANTY; without even the implied warranty of
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27 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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28 GNU General Public License for more details.
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30 You should have received a copy of the GNU General Public License
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31 along with FreeRTOS.org; if not, write to the Free Software
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32 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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34 A special exception to the GPL can be applied should you wish to distribute
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35 a combined work that includes FreeRTOS.org, without being obliged to provide
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36 the source code for any proprietary components. See the licensing section
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37 of http://www.FreeRTOS.org for full details of how and when the exception
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40 ***************************************************************************
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41 ***************************************************************************
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43 * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
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44 * and even write all or part of your application on your behalf. *
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45 * See http://www.OpenRTOS.com for details of the services we provide to *
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46 * expedite your project. *
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48 ***************************************************************************
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49 ***************************************************************************
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51 Please ensure to read the configuration and relevant port sections of the
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52 online documentation.
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54 http://www.FreeRTOS.org - Documentation, latest information, license and
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57 http://www.SafeRTOS.com - A version that is certified for use in safety
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60 http://www.OpenRTOS.com - Commercial support, development, porting,
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61 licensing and training services.
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65 /* Scheduler includes. */
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66 #include "FreeRTOS.h"
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69 /* AVR32 UC3 includes. */
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70 #include <avr32/io.h>
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71 #include <intrinsics.h>
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78 #if( configTICK_USE_TC==1 )
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83 /* Constants required to setup the task context. */
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84 #define portINITIAL_SR ( ( portSTACK_TYPE ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
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85 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 0 )
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87 /* Each task maintains its own critical nesting variable. */
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88 #define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
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89 volatile unsigned portLONG ulCriticalNesting = 9999UL;
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91 #if( configTICK_USE_TC==0 )
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92 static void prvScheduleNextTick( void );
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94 static void prvClearTcInt( void );
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97 /* Setup the timer to generate the tick interrupts. */
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98 static void prvSetupTimerInterrupt( void );
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100 /*-----------------------------------------------------------*/
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103 * Low-level initialization routine called during startup, before the main
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106 int __low_level_init(void)
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108 #if configHEAP_INIT
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109 #pragma segment = "HEAP"
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110 portBASE_TYPE *pxMem;
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113 /* Enable exceptions. */
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114 ENABLE_ALL_EXCEPTIONS();
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116 /* Initialize interrupt handling. */
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117 INTC_init_interrupts();
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119 #if configHEAP_INIT
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121 /* Initialize the heap used by malloc. */
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122 for( pxMem = __segment_begin( "HEAP" ); pxMem < ( portBASE_TYPE * ) __segment_end( "HEAP" ); )
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124 *pxMem++ = 0xA5A5A5A5;
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129 /* Code section present if and only if the debug trace is activated. */
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132 static const gpio_map_t DBG_USART_GPIO_MAP =
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134 { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
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135 { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
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138 static const usart_options_t DBG_USART_OPTIONS =
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140 .baudrate = configDBG_USART_BAUDRATE,
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142 .paritytype = USART_NO_PARITY,
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143 .stopbits = USART_1_STOPBIT,
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144 .channelmode = USART_NORMAL_CHMODE
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147 /* Initialize the USART used for the debug trace with the configured parameters. */
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148 extern volatile avr32_usart_t *volatile stdio_usart_base;
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149 stdio_usart_base = configDBG_USART;
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150 gpio_enable_module( DBG_USART_GPIO_MAP,
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151 sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
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152 usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);
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156 /* Request initialization of data segments. */
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159 /*-----------------------------------------------------------*/
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161 /* Added as there is no such function in FreeRTOS. */
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162 void *pvPortRealloc( void *pv, size_t xWantedSize )
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168 pvReturn = realloc( pv, xWantedSize );
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174 /*-----------------------------------------------------------*/
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176 /* The cooperative scheduler requires a normal IRQ service routine to
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177 simply increment the system tick. */
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178 /* The preemptive scheduler is defined as "naked" as the full context is saved
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179 on entry as part of the context switch. */
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180 #pragma shadow_registers = full // Naked.
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181 static void vTick( void )
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183 /* Save the context of the interrupted task. */
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184 portSAVE_CONTEXT_OS_INT();
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186 #if( configTICK_USE_TC==1 )
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187 /* Clear the interrupt flag. */
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190 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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191 clock cycles from now. */
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192 prvScheduleNextTick();
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195 /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
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196 calls in a critical section . */
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197 portENTER_CRITICAL();
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198 vTaskIncrementTick();
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199 portEXIT_CRITICAL();
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201 /* Restore the context of the "elected task". */
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202 portRESTORE_CONTEXT_OS_INT();
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204 /*-----------------------------------------------------------*/
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206 #pragma shadow_registers = full // Naked.
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207 void SCALLYield( void )
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209 /* Save the context of the interrupted task. */
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210 portSAVE_CONTEXT_SCALL();
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211 vTaskSwitchContext();
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212 portRESTORE_CONTEXT_SCALL();
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214 /*-----------------------------------------------------------*/
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216 /* The code generated by the GCC compiler uses the stack in different ways at
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217 different optimisation levels. The interrupt flags can therefore not always
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218 be saved to the stack. Instead the critical section nesting level is stored
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219 in a variable, which is then saved as part of the stack context. */
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220 #pragma optimize = no_inline
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221 void vPortEnterCritical( void )
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223 /* Disable interrupts */
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224 portDISABLE_INTERRUPTS();
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226 /* Now interrupts are disabled ulCriticalNesting can be accessed
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227 directly. Increment ulCriticalNesting to keep a count of how many times
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228 portENTER_CRITICAL() has been called. */
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229 ulCriticalNesting++;
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231 /*-----------------------------------------------------------*/
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233 #pragma optimize = no_inline
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234 void vPortExitCritical( void )
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236 if(ulCriticalNesting > portNO_CRITICAL_NESTING)
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238 ulCriticalNesting--;
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239 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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241 /* Enable all interrupt/exception. */
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242 portENABLE_INTERRUPTS();
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246 /*-----------------------------------------------------------*/
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249 * Initialise the stack of a task to look exactly as if a call to
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250 * portSAVE_CONTEXT had been called.
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252 * See header file for description.
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254 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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256 /* Setup the initial stack of the task. The stack is set exactly as
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257 expected by the portRESTORE_CONTEXT() macro. */
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259 /* When the task starts, it will expect to find the function parameter in R12. */
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261 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x08080808; /* R8 */
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262 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x09090909; /* R9 */
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263 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0A0A0A0A; /* R10 */
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264 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0B0B0B0B; /* R11 */
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265 *pxTopOfStack-- = ( portSTACK_TYPE ) pvParameters; /* R12 */
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266 *pxTopOfStack-- = ( portSTACK_TYPE ) 0xDEADBEEF; /* R14/LR */
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267 *pxTopOfStack-- = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
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268 *pxTopOfStack-- = ( portSTACK_TYPE ) portINITIAL_SR; /* SR */
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269 *pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF0000FF; /* R0 */
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270 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x01010101; /* R1 */
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271 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x02020202; /* R2 */
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272 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x03030303; /* R3 */
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273 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x04040404; /* R4 */
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274 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x05050505; /* R5 */
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275 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x06060606; /* R6 */
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276 *pxTopOfStack-- = ( portSTACK_TYPE ) 0x07070707; /* R7 */
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277 *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_NESTING; /* ulCriticalNesting */
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279 return pxTopOfStack;
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281 /*-----------------------------------------------------------*/
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283 portBASE_TYPE xPortStartScheduler( void )
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285 /* Start the timer that generates the tick ISR. Interrupts are disabled
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287 prvSetupTimerInterrupt();
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289 /* Start the first task. */
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290 portRESTORE_CONTEXT();
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292 /* Should not get here! */
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295 /*-----------------------------------------------------------*/
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297 void vPortEndScheduler( void )
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299 /* It is unlikely that the AVR32 port will require this function as there
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300 is nothing to return to. */
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302 /*-----------------------------------------------------------*/
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304 /* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
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305 clock cycles from now. */
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306 #if( configTICK_USE_TC==0 )
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307 static void prvScheduleFirstTick(void)
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309 unsigned long lCycles;
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311 lCycles = Get_system_register(AVR32_COUNT);
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312 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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313 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
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314 // generation feature does not get disabled.
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319 Set_system_register(AVR32_COMPARE, lCycles);
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322 #pragma optimize = no_inline
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323 static void prvScheduleNextTick(void)
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325 unsigned long lCycles, lCount;
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327 lCycles = Get_system_register(AVR32_COMPARE);
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328 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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329 // If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
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330 // generation feature does not get disabled.
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335 lCount = Get_system_register(AVR32_COUNT);
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336 if( lCycles < lCount )
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337 { // We missed a tick, recover for the next.
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338 lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
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340 Set_system_register(AVR32_COMPARE, lCycles);
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343 #pragma optimize = no_inline
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344 static void prvClearTcInt(void)
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346 AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
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349 /*-----------------------------------------------------------*/
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351 /* Setup the timer to generate the tick interrupts. */
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352 static void prvSetupTimerInterrupt(void)
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354 #if( configTICK_USE_TC==1 )
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356 volatile avr32_tc_t *tc = &AVR32_TC;
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358 // Options for waveform genration.
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359 tc_waveform_opt_t waveform_opt =
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361 .channel = configTICK_TC_CHANNEL, /* Channel selection. */
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363 .bswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOB. */
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364 .beevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOB. */
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365 .bcpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOB. */
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366 .bcpb = TC_EVT_EFFECT_NOOP, /* RB compare effect on TIOB. */
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368 .aswtrg = TC_EVT_EFFECT_NOOP, /* Software trigger effect on TIOA. */
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369 .aeevt = TC_EVT_EFFECT_NOOP, /* External event effect on TIOA. */
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370 .acpc = TC_EVT_EFFECT_NOOP, /* RC compare effect on TIOA: toggle. */
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371 .acpa = TC_EVT_EFFECT_NOOP, /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
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373 .wavsel = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
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374 .enetrg = FALSE, /* External event trigger enable. */
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375 .eevt = 0, /* External event selection. */
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376 .eevtedg = TC_SEL_NO_EDGE, /* External event edge selection. */
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377 .cpcdis = FALSE, /* Counter disable when RC compare. */
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378 .cpcstop = FALSE, /* Counter clock stopped with RC compare. */
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380 .burst = FALSE, /* Burst signal selection. */
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381 .clki = FALSE, /* Clock inversion. */
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382 .tcclks = TC_CLOCK_SOURCE_TC2 /* Internal source clock 2. */
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385 tc_interrupt_t tc_interrupt =
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399 /* Disable all interrupt/exception. */
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400 portDISABLE_INTERRUPTS();
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402 /* Register the compare interrupt handler to the interrupt controller and
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403 enable the compare interrupt. */
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405 #if( configTICK_USE_TC==1 )
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407 INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0);
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409 /* Initialize the timer/counter. */
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410 tc_init_waveform(tc, &waveform_opt);
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412 /* Set the compare triggers.
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413 Remember TC counter is 16-bits, so counting second is not possible!
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414 That's why we configure it to count ms. */
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415 tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
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417 tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
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419 /* Start the timer/counter. */
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420 tc_start(tc, configTICK_TC_CHANNEL);
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424 INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
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425 prvScheduleFirstTick();
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