1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port header for AVR32 UC3.
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6 * - Compiler: IAR EWAVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support email: avr32@atmel.com
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13 *****************************************************************************/
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16 FreeRTOS.org V4.2.1 - Copyright (C) 2003-2007 Richard Barry.
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18 This file is part of the FreeRTOS.org distribution.
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20 FreeRTOS.org is free software; you can redistribute it and/or modify
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21 it under the terms of the GNU General Public License as published by
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22 the Free Software Foundation; either version 2 of the License, or
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23 (at your option) any later version.
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25 FreeRTOS.org is distributed in the hope that it will be useful,
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26 but WITHOUT ANY WARRANTY; without even the implied warranty of
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27 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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28 GNU General Public License for more details.
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30 You should have received a copy of the GNU General Public License
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31 along with FreeRTOS.org; if not, write to the Free Software
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32 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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34 A special exception to the GPL can be applied should you wish to distribute
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35 a combined work that includes FreeRTOS.org, without being obliged to provide
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36 the source code for any proprietary components. See the licensing section
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37 of http://www.FreeRTOS.org for full details of how and when the exception
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40 ***************************************************************************
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41 See http://www.FreeRTOS.org for documentation, latest information, license
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42 and contact details. Please ensure to read the configuration and relevant
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43 port sections of the online documentation.
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45 Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
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46 with commercial development and support options.
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47 ***************************************************************************
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55 /*-----------------------------------------------------------
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56 * Port specific definitions.
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58 * The settings in this file configure FreeRTOS correctly for the
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59 * given hardware and compiler.
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61 * These settings should not be altered.
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62 *-----------------------------------------------------------
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64 #include <avr32/iouc3a0512.h>
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66 #include "compiler.h"
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69 /* Type definitions. */
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70 #define portCHAR char
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71 #define portFLOAT float
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72 #define portDOUBLE double
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73 #define portLONG long
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74 #define portSHORT short
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75 #define portSTACK_TYPE unsigned portLONG
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76 #define portBASE_TYPE portLONG
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78 #define TASK_DELAY_MS(x) ( (x) /portTICK_RATE_MS )
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79 #define TASK_DELAY_S(x) ( (x)*1000 /portTICK_RATE_MS )
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80 #define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_RATE_MS )
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82 #define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
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84 #if( configUSE_16_BIT_TICKS == 1 )
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85 typedef unsigned portSHORT portTickType;
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86 #define portMAX_DELAY ( portTickType ) 0xffff
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88 typedef unsigned portLONG portTickType;
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89 #define portMAX_DELAY ( portTickType ) 0xffffffff
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91 /*-----------------------------------------------------------*/
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93 /* Architecture specifics. */
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94 #define portSTACK_GROWTH ( -1 )
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95 #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
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96 #define portBYTE_ALIGNMENT 4
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97 #define portNOP() {__asm__ __volatile__ ("nop");}
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98 /*-----------------------------------------------------------*/
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101 /*-----------------------------------------------------------*/
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103 /* INTC-specific. */
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104 #define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
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105 #define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
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107 #define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
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108 #define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
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110 #define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
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111 #define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
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116 * Activated if and only if configDBG is nonzero.
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117 * Prints a formatted string to stdout.
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118 * The current source file name and line number are output with a colon before
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119 * the formatted string.
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120 * A carriage return and a linefeed are appended to the output.
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121 * stdout is redirected by Newlib to the USART configured by configDBG_USART.
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122 * The parameters are the same as for the standard printf function.
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123 * There is no return value.
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124 * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
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125 * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
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128 #define portDBG_TRACE(...) \
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130 fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout); \
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131 printf(__VA_ARGS__); \
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132 fputs("\r\n", stdout); \
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135 #define portDBG_TRACE(...)
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139 /* Critical section management. */
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140 #define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
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141 #define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
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144 extern void vPortEnterCritical( void );
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145 extern void vPortExitCritical( void );
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147 #define portENTER_CRITICAL() vPortEnterCritical();
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148 #define portEXIT_CRITICAL() vPortExitCritical();
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151 /* Added as there is no such function in FreeRTOS. */
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152 extern void *pvPortRealloc( void *pv, size_t xSize );
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153 /*-----------------------------------------------------------*/
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156 /*=============================================================================================*/
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159 * Restore Context for cases other than INTi.
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161 #define portRESTORE_CONTEXT() \
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163 extern volatile unsigned portLONG ulCriticalNesting; \
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164 extern volatile void *volatile pxCurrentTCB; \
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166 __asm__ __volatile__ ( \
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167 /* Set SP to point to new stack */ \
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168 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
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169 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
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170 "ld.w r0, r8[0] \n\t"\
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171 "ld.w sp, r0[0] \n\t"\
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173 /* Restore ulCriticalNesting variable */ \
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174 "ld.w r0, sp++ \n\t"\
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175 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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176 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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177 "st.w r8[0], r0 \n\t"\
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179 /* Restore R0..R7 */ \
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180 "ldm sp++, r0-r7 \n\t"\
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181 /* R0-R7 should not be used below this line */ \
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182 /* Skip PC and SR (will do it at the end) */ \
\r
183 "sub sp, -2*4 \n\t"\
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184 /* Restore R8..R12 and LR */ \
\r
185 "ldm sp++, r8-r12, lr \n\t"\
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187 "ld.w r0, sp[-8*4] \n\t" /* R0 is modified, is restored later. */\
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188 "mtsr "ASTRINGZ(AVR32_SR)", r0 \n\t"\
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190 "ld.w r0, sp[-9*4] \n\t"\
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192 "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
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195 /* Force import of global symbols from assembly */ \
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196 ulCriticalNesting; \
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202 * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
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203 * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
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205 * Had to make different versions because registers saved on the system stack
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206 * are not the same between INT0..3 exceptions and the scall exception.
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209 // Task context stack layout:
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226 // ulCriticalNesting
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227 // (*) automatically done for INT0..INT3, but not for SCALL
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230 * The ISR used for the scheduler tick depends on whether the cooperative or
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231 * the preemptive scheduler is being used.
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233 #if configUSE_PREEMPTION == 0
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236 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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238 #define portSAVE_CONTEXT_OS_INT() \
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240 /* Save R0..R7 */ \
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241 __asm__ __volatile__ ("stm --sp, r0-r7"); \
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243 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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244 /* there is also no context save. */ \
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248 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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250 #define portRESTORE_CONTEXT_OS_INT() \
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252 __asm__ __volatile__ ( \
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253 /* Restore R0..R7 */ \
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254 "ldm sp++, r0-r7 \n\t"\
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256 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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257 /* there is also no context restore. */ \
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265 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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267 #define portSAVE_CONTEXT_OS_INT() \
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269 extern volatile unsigned portLONG ulCriticalNesting; \
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270 extern volatile void *volatile pxCurrentTCB; \
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272 /* When we come here */ \
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273 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
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275 __asm__ __volatile__ ( \
\r
276 /* Save R0..R7 */ \
\r
277 "stm --sp, r0-r7 \n\t"\
\r
279 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
280 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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281 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
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282 "ld.w r0, r8[0] \n\t"\
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283 "st.w --sp, r0 \n\t"\
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285 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
286 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
287 /* level and allow other lower interrupt level to occur). */ \
\r
288 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
289 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
290 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
291 /* will just be restoring the interrupt handler, no way!!! */ \
\r
292 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
293 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
294 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
295 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
296 "brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
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298 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
299 /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
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300 /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
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301 /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
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302 /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
\r
303 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
304 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
305 "ld.w r0, r8[0] \n\t"\
\r
306 "st.w r0[0], sp \n"\
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308 "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
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313 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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315 #define portRESTORE_CONTEXT_OS_INT() \
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317 extern volatile unsigned portLONG ulCriticalNesting; \
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318 extern volatile void *volatile pxCurrentTCB; \
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320 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
321 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
322 /* level and allow other lower interrupt level to occur). */ \
\r
323 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
324 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
325 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
326 /* will just be restoring the interrupt handler, no way!!! */ \
\r
327 __asm__ __volatile__ ( \
\r
328 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
329 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
330 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
331 "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__) \
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335 /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
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336 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
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337 portENTER_CRITICAL(); \
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338 vTaskSwitchContext(); \
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339 portEXIT_CRITICAL(); \
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341 /* Restore all registers */ \
\r
343 __asm__ __volatile__ ( \
\r
344 /* Set SP to point to new stack */ \
\r
345 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
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346 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
347 "ld.w r0, r8[0] \n\t"\
\r
348 "ld.w sp, r0[0] \n"\
\r
350 "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
\r
352 /* Restore ulCriticalNesting variable */ \
\r
353 "ld.w r0, sp++ \n\t"\
\r
354 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
355 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
356 "st.w r8[0], r0 \n\t"\
\r
358 /* Restore R0..R7 */ \
\r
359 "ldm sp++, r0-r7 \n\t"\
\r
361 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
365 /* Force import of global symbols from assembly */ \
\r
366 ulCriticalNesting; \
\r
374 * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
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376 * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
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379 #define portSAVE_CONTEXT_SCALL() \
\r
381 extern volatile unsigned portLONG ulCriticalNesting; \
\r
382 extern volatile void *volatile pxCurrentTCB; \
\r
384 /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
\r
385 /* If SR[M2:M0] == 001 */ \
\r
386 /* PC and SR are on the stack. */ \
\r
387 /* Else (other modes) */ \
\r
388 /* Nothing on the stack. */ \
\r
390 /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
\r
391 /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
\r
392 /* in an interrupt|exception handler. */ \
\r
394 __asm__ __volatile__ ( \
\r
395 /* in order to save R0-R7 */ \
\r
396 "sub sp, 6*4 \n\t"\
\r
397 /* Save R0..R7 */ \
\r
398 "stm --sp, r0-r7 \n\t"\
\r
400 /* in order to save R8-R12 and LR */ \
\r
401 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
402 "sub r7, sp,-16*4 \n\t"\
\r
403 /* Copy PC and SR in other places in the stack. */ \
\r
404 "ld.w r0, r7[-2*4] \n\t" /* Read SR */\
\r
405 "st.w r7[-8*4], r0 \n\t" /* Copy SR */\
\r
406 "ld.w r0, r7[-1*4] \n\t" /* Read PC */\
\r
407 "st.w r7[-7*4], r0 \n\t" /* Copy PC */\
\r
409 /* Save R8..R12 and LR on the stack. */ \
\r
410 "stm --r7, r8-r12, lr \n\t"\
\r
412 /* Arriving here we have the following stack organizations: */ \
\r
413 /* R8..R12, LR, PC, SR, R0..R7. */ \
\r
415 /* Now we can finalize the save. */ \
\r
417 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
418 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
419 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
420 "ld.w r0, r8[0] \n\t"\
\r
424 /* Disable the its which may cause a context switch (i.e. cause a change of */ \
\r
425 /* pxCurrentTCB). */ \
\r
426 /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
\r
427 /* critical section because it is a global structure. */ \
\r
428 portENTER_CRITICAL(); \
\r
430 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
431 __asm__ __volatile__ ( \
\r
432 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
433 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
434 "ld.w r0, r8[0] \n\t"\
\r
440 * portRESTORE_CONTEXT() for SupervisorCALL exception.
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442 #define portRESTORE_CONTEXT_SCALL() \
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444 extern volatile unsigned portLONG ulCriticalNesting; \
\r
445 extern volatile void *volatile pxCurrentTCB; \
\r
447 /* Restore all registers */ \
\r
449 /* Set SP to point to new stack */ \
\r
450 __asm__ __volatile__ ( \
\r
451 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
452 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
453 "ld.w r0, r8[0] \n\t"\
\r
457 /* Leave pxCurrentTCB variable access critical section */ \
\r
458 portEXIT_CRITICAL(); \
\r
460 __asm__ __volatile__ ( \
\r
461 /* Restore ulCriticalNesting variable */ \
\r
462 "ld.w r0, sp++ \n\t"\
\r
463 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
464 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
465 "st.w r8[0], r0 \n\t"\
\r
467 /* skip PC and SR */ \
\r
468 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
469 "sub r7, sp, -10*4 \n\t"\
\r
470 /* Restore r8-r12 and LR */ \
\r
471 "ldm r7++, r8-r12, lr \n\t"\
\r
473 /* RETS will take care of the extra PC and SR restore. */ \
\r
474 /* So, we have to prepare the stack for this. */ \
\r
475 "ld.w r0, r7[-8*4] \n\t" /* Read SR */\
\r
476 "st.w r7[-2*4], r0 \n\t" /* Copy SR */\
\r
477 "ld.w r0, r7[-7*4] \n\t" /* Read PC */\
\r
478 "st.w r7[-1*4], r0 \n\t" /* Copy PC */\
\r
480 /* Restore R0..R7 */ \
\r
481 "ldm sp++, r0-r7 \n\t"\
\r
483 "sub sp, -6*4 \n\t"\
\r
488 /* Force import of global symbols from assembly */ \
\r
489 ulCriticalNesting; \
\r
495 * The ISR used depends on whether the cooperative or
\r
496 * the preemptive scheduler is being used.
\r
498 #if configUSE_PREEMPTION == 0
\r
501 * ISR entry and exit macros. These are only required if a task switch
\r
502 * is required from the ISR.
\r
504 #define portENTER_SWITCHING_ISR() \
\r
506 /* Save R0..R7 */ \
\r
507 __asm__ __volatile__ ("stm --sp, r0-r7"); \
\r
509 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
510 /* there is also no context save. */ \
\r
514 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
516 #define portEXIT_SWITCHING_ISR() \
\r
518 __asm__ __volatile__ ( \
\r
519 /* Restore R0..R7 */ \
\r
520 "ldm sp++, r0-r7 \n\t"\
\r
522 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
523 /* there is also no context restore. */ \
\r
531 * ISR entry and exit macros. These are only required if a task switch
\r
532 * is required from the ISR.
\r
534 #define portENTER_SWITCHING_ISR() \
\r
536 extern volatile unsigned portLONG ulCriticalNesting; \
\r
537 extern volatile void *volatile pxCurrentTCB; \
\r
539 /* When we come here */ \
\r
540 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
\r
542 __asm__ __volatile__ ( \
\r
543 /* Save R0..R7 */ \
\r
544 "stm --sp, r0-r7 \n\t"\
\r
546 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
547 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
548 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
549 "ld.w r0, r8[0] \n\t"\
\r
550 "st.w --sp, r0 \n\t"\
\r
552 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
553 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
554 /* level and allow other lower interrupt level to occur). */ \
\r
555 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
556 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
557 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
558 /* will just be restoring the interrupt handler, no way!!! */ \
\r
559 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
560 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
561 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
562 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
563 "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
\r
565 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
566 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
567 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
568 "ld.w r0, r8[0] \n\t"\
\r
569 "st.w r0[0], sp \n"\
\r
571 "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
\r
577 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
579 #define portEXIT_SWITCHING_ISR() \
\r
581 extern volatile unsigned portLONG ulCriticalNesting; \
\r
582 extern volatile void *volatile pxCurrentTCB; \
\r
584 __asm__ __volatile__ ( \
\r
585 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
586 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
587 /* level and allow other lower interrupt level to occur). */ \
\r
588 /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
\r
589 /* did not previously save SP in its TCB. */ \
\r
590 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
591 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
592 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
593 "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
\r
595 /* If a switch is required then we just need to call */ \
\r
596 /* vTaskSwitchContext() as the context has already been */ \
\r
598 "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
\r
599 "brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C" \
\r
602 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
\r
603 portENTER_CRITICAL(); \
\r
604 vTaskSwitchContext(); \
\r
605 portEXIT_CRITICAL(); \
\r
607 __asm__ __volatile__ ( \
\r
608 "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
\r
609 /* Restore the context of which ever task is now the highest */ \
\r
610 /* priority that is ready to run. */ \
\r
612 /* Restore all registers */ \
\r
614 /* Set SP to point to new stack */ \
\r
615 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
616 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
617 "ld.w r0, r8[0] \n\t"\
\r
618 "ld.w sp, r0[0] \n"\
\r
620 "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
\r
622 /* Restore ulCriticalNesting variable */ \
\r
623 "ld.w r0, sp++ \n\t"\
\r
624 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
625 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
626 "st.w r8[0], r0 \n\t"\
\r
628 /* Restore R0..R7 */ \
\r
629 "ldm sp++, r0-r7 \n\t"\
\r
631 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
635 /* Force import of global symbols from assembly */ \
\r
636 ulCriticalNesting; \
\r
643 #define portYIELD() {__asm__ __volatile__ ("scall");}
\r
645 /* Task function macros as described on the FreeRTOS.org WEB site. */
\r
646 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
647 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
651 #endif /* PORTMACRO_H */
\r
projects / freertos / blob