1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port header for AVR32 UC3.
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6 * - Compiler: IAR EWAVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support and FAQ: http://support.atmel.no/
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13 *****************************************************************************/
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16 FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.
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19 ***************************************************************************
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21 * FreeRTOS tutorial books are available in pdf and paperback. *
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22 * Complete, revised, and edited pdf reference manuals are also *
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25 * Purchasing FreeRTOS documentation will not only help you, by *
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26 * ensuring you get running as quickly as possible and with an *
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27 * in-depth knowledge of how to use FreeRTOS, it will also help *
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28 * the FreeRTOS project to continue with its mission of providing *
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29 * professional grade, cross platform, de facto standard solutions *
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30 * for microcontrollers - completely free of charge! *
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32 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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34 * Thank you for using FreeRTOS, and thank you for your support! *
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36 ***************************************************************************
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39 This file is part of the FreeRTOS distribution.
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41 FreeRTOS is free software; you can redistribute it and/or modify it under
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42 the terms of the GNU General Public License (version 2) as published by the
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43 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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44 >>>NOTE<<< The modification to the GPL is included to allow you to
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45 distribute a combined work that includes FreeRTOS without being obliged to
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46 provide the source code for proprietary components outside of the FreeRTOS
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47 kernel. FreeRTOS is distributed in the hope that it will be useful, but
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48 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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49 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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50 more details. You should have received a copy of the GNU General Public
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51 License and the FreeRTOS license exception along with FreeRTOS; if not it
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52 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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53 by writing to Richard Barry, contact details for whom are available on the
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58 http://www.FreeRTOS.org - Documentation, latest information, license and
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61 http://www.SafeRTOS.com - A version that is certified for use in safety
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64 http://www.OpenRTOS.com - Commercial support, development, porting,
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65 licensing and training services.
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73 /*-----------------------------------------------------------
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74 * Port specific definitions.
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76 * The settings in this file configure FreeRTOS correctly for the
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77 * given hardware and compiler.
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79 * These settings should not be altered.
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80 *-----------------------------------------------------------
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82 #include <avr32/io.h>
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84 #include "compiler.h"
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91 /* Type definitions. */
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92 #define portCHAR char
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93 #define portFLOAT float
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94 #define portDOUBLE double
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95 #define portLONG long
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96 #define portSHORT short
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97 #define portSTACK_TYPE unsigned portLONG
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98 #define portBASE_TYPE portLONG
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100 #define TASK_DELAY_MS(x) ( (x) /portTICK_RATE_MS )
\r
101 #define TASK_DELAY_S(x) ( (x)*1000 /portTICK_RATE_MS )
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102 #define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_RATE_MS )
\r
104 #define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
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106 #if( configUSE_16_BIT_TICKS == 1 )
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107 typedef unsigned portSHORT portTickType;
\r
108 #define portMAX_DELAY ( portTickType ) 0xffff
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110 typedef unsigned portLONG portTickType;
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111 #define portMAX_DELAY ( portTickType ) 0xffffffff
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113 /*-----------------------------------------------------------*/
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115 /* Architecture specifics. */
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116 #define portSTACK_GROWTH ( -1 )
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117 #define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
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118 #define portBYTE_ALIGNMENT 4
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119 #define portNOP() {__asm__ __volatile__ ("nop");}
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120 /*-----------------------------------------------------------*/
\r
123 /*-----------------------------------------------------------*/
\r
125 /* INTC-specific. */
\r
126 #define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
\r
127 #define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
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129 #define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
\r
130 #define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
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132 #define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
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133 #define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
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138 * Activated if and only if configDBG is nonzero.
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139 * Prints a formatted string to stdout.
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140 * The current source file name and line number are output with a colon before
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141 * the formatted string.
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142 * A carriage return and a linefeed are appended to the output.
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143 * stdout is redirected to the USART configured by configDBG_USART.
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144 * The parameters are the same as for the standard printf function.
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145 * There is no return value.
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146 * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
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147 * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
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150 #define portDBG_TRACE(...) \
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152 fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout); \
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153 printf(__VA_ARGS__); \
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154 fputs("\r\n", stdout); \
\r
157 #define portDBG_TRACE(...)
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161 /* Critical section management. */
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162 #define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
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163 #define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
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166 extern void vPortEnterCritical( void );
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167 extern void vPortExitCritical( void );
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169 #define portENTER_CRITICAL() vPortEnterCritical();
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170 #define portEXIT_CRITICAL() vPortExitCritical();
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173 /* Added as there is no such function in FreeRTOS. */
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174 extern void *pvPortRealloc( void *pv, size_t xSize );
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175 /*-----------------------------------------------------------*/
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178 /*=============================================================================================*/
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181 * Restore Context for cases other than INTi.
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183 #define portRESTORE_CONTEXT() \
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185 extern volatile unsigned portLONG ulCriticalNesting; \
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186 extern volatile void *volatile pxCurrentTCB; \
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188 __asm__ __volatile__ ( \
\r
189 /* Set SP to point to new stack */ \
\r
190 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
191 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
192 "ld.w r0, r8[0] \n\t"\
\r
193 "ld.w sp, r0[0] \n\t"\
\r
195 /* Restore ulCriticalNesting variable */ \
\r
196 "ld.w r0, sp++ \n\t"\
\r
197 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
198 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
199 "st.w r8[0], r0 \n\t"\
\r
201 /* Restore R0..R7 */ \
\r
202 "ldm sp++, r0-r7 \n\t"\
\r
203 /* R0-R7 should not be used below this line */ \
\r
204 /* Skip PC and SR (will do it at the end) */ \
\r
205 "sub sp, -2*4 \n\t"\
\r
206 /* Restore R8..R12 and LR */ \
\r
207 "ldm sp++, r8-r12, lr \n\t"\
\r
209 "ld.w r0, sp[-8*4] \n\t" /* R0 is modified, is restored later. */\
\r
210 "mtsr "ASTRINGZ(AVR32_SR)", r0 \n\t"\
\r
212 "ld.w r0, sp[-9*4] \n\t"\
\r
214 "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
\r
217 /* Force import of global symbols from assembly */ \
\r
218 ulCriticalNesting; \
\r
224 * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
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225 * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
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227 * Had to make different versions because registers saved on the system stack
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228 * are not the same between INT0..3 exceptions and the scall exception.
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231 // Task context stack layout:
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248 // ulCriticalNesting
\r
249 // (*) automatically done for INT0..INT3, but not for SCALL
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252 * The ISR used for the scheduler tick depends on whether the cooperative or
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253 * the preemptive scheduler is being used.
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255 #if configUSE_PREEMPTION == 0
\r
258 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
\r
260 #define portSAVE_CONTEXT_OS_INT() \
\r
262 /* Save R0..R7 */ \
\r
263 __asm__ __volatile__ ("stm --sp, r0-r7"); \
\r
265 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
266 /* there is also no context save. */ \
\r
270 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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272 #define portRESTORE_CONTEXT_OS_INT() \
\r
274 __asm__ __volatile__ ( \
\r
275 /* Restore R0..R7 */ \
\r
276 "ldm sp++, r0-r7 \n\t"\
\r
278 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
279 /* there is also no context restore. */ \
\r
287 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
\r
289 #define portSAVE_CONTEXT_OS_INT() \
\r
291 extern volatile unsigned portLONG ulCriticalNesting; \
\r
292 extern volatile void *volatile pxCurrentTCB; \
\r
294 /* When we come here */ \
\r
295 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
\r
297 __asm__ __volatile__ ( \
\r
298 /* Save R0..R7 */ \
\r
299 "stm --sp, r0-r7 \n\t"\
\r
301 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
302 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
303 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
304 "ld.w r0, r8[0] \n\t"\
\r
305 "st.w --sp, r0 \n\t"\
\r
307 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
308 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
309 /* level and allow other lower interrupt level to occur). */ \
\r
310 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
311 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
312 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
313 /* will just be restoring the interrupt handler, no way!!! */ \
\r
314 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
315 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
316 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
317 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
318 "brhi LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
\r
320 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
321 /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
\r
322 /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
\r
323 /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
\r
324 /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
\r
325 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
326 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
327 "ld.w r0, r8[0] \n\t"\
\r
328 "st.w r0[0], sp \n"\
\r
330 "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
\r
335 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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337 #define portRESTORE_CONTEXT_OS_INT() \
\r
339 extern volatile unsigned portLONG ulCriticalNesting; \
\r
340 extern volatile void *volatile pxCurrentTCB; \
\r
342 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
343 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
344 /* level and allow other lower interrupt level to occur). */ \
\r
345 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
346 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
347 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
348 /* will just be restoring the interrupt handler, no way!!! */ \
\r
349 __asm__ __volatile__ ( \
\r
350 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
351 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
352 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
353 "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__) \
\r
357 /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
\r
358 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
\r
359 portENTER_CRITICAL(); \
\r
360 vTaskSwitchContext(); \
\r
361 portEXIT_CRITICAL(); \
\r
363 /* Restore all registers */ \
\r
365 __asm__ __volatile__ ( \
\r
366 /* Set SP to point to new stack */ \
\r
367 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
368 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
369 "ld.w r0, r8[0] \n\t"\
\r
370 "ld.w sp, r0[0] \n"\
\r
372 "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
\r
374 /* Restore ulCriticalNesting variable */ \
\r
375 "ld.w r0, sp++ \n\t"\
\r
376 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
377 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
378 "st.w r8[0], r0 \n\t"\
\r
380 /* Restore R0..R7 */ \
\r
381 "ldm sp++, r0-r7 \n\t"\
\r
383 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
387 /* Force import of global symbols from assembly */ \
\r
388 ulCriticalNesting; \
\r
396 * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
\r
398 * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
\r
401 #define portSAVE_CONTEXT_SCALL() \
\r
403 extern volatile unsigned portLONG ulCriticalNesting; \
\r
404 extern volatile void *volatile pxCurrentTCB; \
\r
406 /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
\r
407 /* If SR[M2:M0] == 001 */ \
\r
408 /* PC and SR are on the stack. */ \
\r
409 /* Else (other modes) */ \
\r
410 /* Nothing on the stack. */ \
\r
412 /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
\r
413 /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
\r
414 /* in an interrupt|exception handler. */ \
\r
416 __asm__ __volatile__ ( \
\r
417 /* in order to save R0-R7 */ \
\r
418 "sub sp, 6*4 \n\t"\
\r
419 /* Save R0..R7 */ \
\r
420 "stm --sp, r0-r7 \n\t"\
\r
422 /* in order to save R8-R12 and LR */ \
\r
423 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
424 "sub r7, sp,-16*4 \n\t"\
\r
425 /* Copy PC and SR in other places in the stack. */ \
\r
426 "ld.w r0, r7[-2*4] \n\t" /* Read SR */\
\r
427 "st.w r7[-8*4], r0 \n\t" /* Copy SR */\
\r
428 "ld.w r0, r7[-1*4] \n\t" /* Read PC */\
\r
429 "st.w r7[-7*4], r0 \n\t" /* Copy PC */\
\r
431 /* Save R8..R12 and LR on the stack. */ \
\r
432 "stm --r7, r8-r12, lr \n\t"\
\r
434 /* Arriving here we have the following stack organizations: */ \
\r
435 /* R8..R12, LR, PC, SR, R0..R7. */ \
\r
437 /* Now we can finalize the save. */ \
\r
439 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
440 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
441 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
442 "ld.w r0, r8[0] \n\t"\
\r
446 /* Disable the its which may cause a context switch (i.e. cause a change of */ \
\r
447 /* pxCurrentTCB). */ \
\r
448 /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
\r
449 /* critical section because it is a global structure. */ \
\r
450 portENTER_CRITICAL(); \
\r
452 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
453 __asm__ __volatile__ ( \
\r
454 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
455 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
456 "ld.w r0, r8[0] \n\t"\
\r
462 * portRESTORE_CONTEXT() for SupervisorCALL exception.
\r
464 #define portRESTORE_CONTEXT_SCALL() \
\r
466 extern volatile unsigned portLONG ulCriticalNesting; \
\r
467 extern volatile void *volatile pxCurrentTCB; \
\r
469 /* Restore all registers */ \
\r
471 /* Set SP to point to new stack */ \
\r
472 __asm__ __volatile__ ( \
\r
473 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
474 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
475 "ld.w r0, r8[0] \n\t"\
\r
479 /* Leave pxCurrentTCB variable access critical section */ \
\r
480 portEXIT_CRITICAL(); \
\r
482 __asm__ __volatile__ ( \
\r
483 /* Restore ulCriticalNesting variable */ \
\r
484 "ld.w r0, sp++ \n\t"\
\r
485 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
486 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
487 "st.w r8[0], r0 \n\t"\
\r
489 /* skip PC and SR */ \
\r
490 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
491 "sub r7, sp, -10*4 \n\t"\
\r
492 /* Restore r8-r12 and LR */ \
\r
493 "ldm r7++, r8-r12, lr \n\t"\
\r
495 /* RETS will take care of the extra PC and SR restore. */ \
\r
496 /* So, we have to prepare the stack for this. */ \
\r
497 "ld.w r0, r7[-8*4] \n\t" /* Read SR */\
\r
498 "st.w r7[-2*4], r0 \n\t" /* Copy SR */\
\r
499 "ld.w r0, r7[-7*4] \n\t" /* Read PC */\
\r
500 "st.w r7[-1*4], r0 \n\t" /* Copy PC */\
\r
502 /* Restore R0..R7 */ \
\r
503 "ldm sp++, r0-r7 \n\t"\
\r
505 "sub sp, -6*4 \n\t"\
\r
510 /* Force import of global symbols from assembly */ \
\r
511 ulCriticalNesting; \
\r
517 * The ISR used depends on whether the cooperative or
\r
518 * the preemptive scheduler is being used.
\r
520 #if configUSE_PREEMPTION == 0
\r
523 * ISR entry and exit macros. These are only required if a task switch
\r
524 * is required from the ISR.
\r
526 #define portENTER_SWITCHING_ISR() \
\r
528 /* Save R0..R7 */ \
\r
529 __asm__ __volatile__ ("stm --sp, r0-r7"); \
\r
531 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
532 /* there is also no context save. */ \
\r
536 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
538 #define portEXIT_SWITCHING_ISR() \
\r
540 __asm__ __volatile__ ( \
\r
541 /* Restore R0..R7 */ \
\r
542 "ldm sp++, r0-r7 \n\t"\
\r
544 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
545 /* there is also no context restore. */ \
\r
553 * ISR entry and exit macros. These are only required if a task switch
\r
554 * is required from the ISR.
\r
556 #define portENTER_SWITCHING_ISR() \
\r
558 extern volatile unsigned portLONG ulCriticalNesting; \
\r
559 extern volatile void *volatile pxCurrentTCB; \
\r
561 /* When we come here */ \
\r
562 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
\r
564 __asm__ __volatile__ ( \
\r
565 /* Save R0..R7 */ \
\r
566 "stm --sp, r0-r7 \n\t"\
\r
568 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
569 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
570 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
571 "ld.w r0, r8[0] \n\t"\
\r
572 "st.w --sp, r0 \n\t"\
\r
574 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
575 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
576 /* level and allow other lower interrupt level to occur). */ \
\r
577 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
578 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
579 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
580 /* will just be restoring the interrupt handler, no way!!! */ \
\r
581 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
582 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
583 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
584 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
585 "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
\r
587 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
588 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
589 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
590 "ld.w r0, r8[0] \n\t"\
\r
591 "st.w r0[0], sp \n"\
\r
593 "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":" \
\r
599 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
601 #define portEXIT_SWITCHING_ISR() \
\r
603 extern volatile unsigned portLONG ulCriticalNesting; \
\r
604 extern volatile void *volatile pxCurrentTCB; \
\r
606 __asm__ __volatile__ ( \
\r
607 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
608 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
609 /* level and allow other lower interrupt level to occur). */ \
\r
610 /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
\r
611 /* did not previously save SP in its TCB. */ \
\r
612 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
613 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
614 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
615 "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)" \n\t"\
\r
617 /* If a switch is required then we just need to call */ \
\r
618 /* vTaskSwitchContext() as the context has already been */ \
\r
620 "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
\r
621 "brne LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C" \
\r
624 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
\r
625 portENTER_CRITICAL(); \
\r
626 vTaskSwitchContext(); \
\r
627 portEXIT_CRITICAL(); \
\r
629 __asm__ __volatile__ ( \
\r
630 "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
\r
631 /* Restore the context of which ever task is now the highest */ \
\r
632 /* priority that is ready to run. */ \
\r
634 /* Restore all registers */ \
\r
636 /* Set SP to point to new stack */ \
\r
637 "mov r8, LWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
638 "orh r8, HWRD("ASTRINGZ(pxCurrentTCB)") \n\t"\
\r
639 "ld.w r0, r8[0] \n\t"\
\r
640 "ld.w sp, r0[0] \n"\
\r
642 "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)": \n\t"\
\r
644 /* Restore ulCriticalNesting variable */ \
\r
645 "ld.w r0, sp++ \n\t"\
\r
646 "mov r8, LWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
647 "orh r8, HWRD("ASTRINGZ(ulCriticalNesting)") \n\t"\
\r
648 "st.w r8[0], r0 \n\t"\
\r
650 /* Restore R0..R7 */ \
\r
651 "ldm sp++, r0-r7 \n\t"\
\r
653 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
657 /* Force import of global symbols from assembly */ \
\r
658 ulCriticalNesting; \
\r
665 #define portYIELD() {__asm__ __volatile__ ("scall");}
\r
667 /* Task function macros as described on the FreeRTOS.org WEB site. */
\r
668 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
669 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
675 #endif /* PORTMACRO_H */
\r