2 FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.
\r
4 This file is part of the FreeRTOS.org distribution.
\r
6 FreeRTOS.org is free software; you can redistribute it and/or modify
\r
7 it under the terms of the GNU General Public License as published by
\r
8 the Free Software Foundation; either version 2 of the License, or
\r
9 (at your option) any later version.
\r
11 FreeRTOS.org is distributed in the hope that it will be useful,
\r
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
\r
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
\r
14 GNU General Public License for more details.
\r
16 You should have received a copy of the GNU General Public License
\r
17 along with FreeRTOS.org; if not, write to the Free Software
\r
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
\r
20 A special exception to the GPL can be applied should you wish to distribute
\r
21 a combined work that includes FreeRTOS.org, without being obliged to provide
\r
22 the source code for any proprietary components. See the licensing section
\r
23 of http://www.FreeRTOS.org for full details of how and when the exception
\r
26 ***************************************************************************
\r
27 ***************************************************************************
\r
29 * SAVE TIME AND MONEY! Why not get us to quote to get FreeRTOS.org *
\r
30 * running on your hardware - or even write all or part of your application*
\r
31 * for you? See http://www.OpenRTOS.com for details. *
\r
33 ***************************************************************************
\r
34 ***************************************************************************
\r
36 Please ensure to read the configuration and relevant port sections of the
\r
37 online documentation.
\r
39 http://www.FreeRTOS.org - Documentation, latest information, license and
\r
42 http://www.SafeRTOS.com - A version that is certified for use in safety
\r
45 http://www.OpenRTOS.com - Commercial support, development, porting,
\r
46 licensing and training services.
\r
49 /*-----------------------------------------------------------
\r
50 * Implementation of functions defined in portable.h for the ST STR71x ARM7
\r
52 *----------------------------------------------------------*/
\r
54 /* Library includes. */
\r
58 /* Standard includes. */
\r
61 /* Scheduler includes. */
\r
62 #include "FreeRTOS.h"
\r
65 /* Constants required to setup the initial stack. */
\r
66 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
\r
67 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
\r
69 /* Constants required to handle critical sections. */
\r
70 #define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
\r
72 #define portMICROS_PER_SECOND 1000000
\r
74 /*-----------------------------------------------------------*/
\r
76 /* Setup the watchdog to generate the tick interrupts. */
\r
77 static void prvSetupTimerInterrupt( void );
\r
79 /* ulCriticalNesting will get set to zero when the first task starts. It
\r
80 cannot be initialised to 0 as this will cause interrupts to be enabled
\r
81 during the kernel initialisation process. */
\r
82 unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999;
\r
84 /* Tick interrupt routines for cooperative and preemptive operation
\r
85 respectively. The preemptive version is not defined as __irq as it is called
\r
86 from an asm wrapper function. */
\r
87 __arm __irq void vPortNonPreemptiveTick( void );
\r
88 void vPortPreemptiveTick( void );
\r
90 /*-----------------------------------------------------------*/
\r
93 * Initialise the stack of a task to look exactly as if a call to
\r
94 * portSAVE_CONTEXT had been called.
\r
96 * See header file for description.
\r
98 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
\r
100 portSTACK_TYPE *pxOriginalTOS;
\r
102 pxOriginalTOS = pxTopOfStack;
\r
104 /* Setup the initial stack of the task. The stack is set exactly as
\r
105 expected by the portRESTORE_CONTEXT() macro. */
\r
107 /* First on the stack is the return address - which in this case is the
\r
108 start of the task. The offset is added to make the return address appear
\r
109 as it would within an IRQ ISR. */
\r
110 *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
\r
113 *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
\r
115 *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
\r
117 *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
\r
119 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
\r
121 *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
\r
123 *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
\r
125 *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
\r
127 *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
\r
129 *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
\r
131 *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
\r
133 *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
\r
135 *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
\r
137 *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
\r
139 *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
\r
142 /* When the task starts is will expect to find the function parameter in
\r
144 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
\r
147 /* The status register is set for system mode, with interrupts enabled. */
\r
148 *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
\r
151 /* Interrupt flags cannot always be stored on the stack and will
\r
152 instead be stored in a variable, which is then saved as part of the
\r
154 *pxTopOfStack = portNO_CRITICAL_NESTING;
\r
156 return pxTopOfStack;
\r
158 /*-----------------------------------------------------------*/
\r
160 portBASE_TYPE xPortStartScheduler( void )
\r
162 extern void vPortStartFirstTask( void );
\r
164 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
166 prvSetupTimerInterrupt();
\r
168 /* Start the first task. */
\r
169 vPortStartFirstTask();
\r
171 /* Should not get here! */
\r
174 /*-----------------------------------------------------------*/
\r
176 void vPortEndScheduler( void )
\r
178 /* It is unlikely that the ARM port will require this function as there
\r
179 is nothing to return to. */
\r
181 /*-----------------------------------------------------------*/
\r
183 /* The cooperative scheduler requires a normal IRQ service routine to
\r
184 simply increment the system tick. */
\r
185 __arm __irq void vPortNonPreemptiveTick( void )
\r
187 /* Increment the tick count - which may wake some tasks but as the
\r
188 preemptive scheduler is not being used any woken task is not given
\r
189 processor time no matter what its priority. */
\r
190 vTaskIncrementTick();
\r
192 /* Clear the interrupt in the watchdog and EIC. */
\r
196 /*-----------------------------------------------------------*/
\r
198 /* This function is called from an asm wrapper, so does not require the __irq
\r
200 void vPortPreemptiveTick( void )
\r
202 /* Increment the tick counter. */
\r
203 vTaskIncrementTick();
\r
205 /* The new tick value might unblock a task. Ensure the highest task that
\r
206 is ready to execute is the task that will execute when the tick ISR
\r
208 vTaskSwitchContext();
\r
210 /* Clear the interrupt in the watchdog and EIC. */
\r
214 /*-----------------------------------------------------------*/
\r
216 static void prvSetupTimerInterrupt( void )
\r
218 /* Set the watchdog up to generate a periodic tick. */
\r
219 WDG_ECITConfig( DISABLE );
\r
220 WDG_CntOnOffConfig( DISABLE );
\r
221 WDG_PeriodValueConfig( portMICROS_PER_SECOND / configTICK_RATE_HZ );
\r
223 /* Setup the tick interrupt in the EIC. */
\r
224 EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 );
\r
225 EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE );
\r
226 EIC_IRQConfig( ENABLE );
\r
227 WDG_ECITConfig( ENABLE );
\r
229 /* Start the timer - interrupts are actually disabled at this point so
\r
230 it is safe to do this here. */
\r
231 WDG_CntOnOffConfig( ENABLE );
\r
233 /*-----------------------------------------------------------*/
\r
235 __arm __interwork void vPortEnterCritical( void )
\r
237 /* Disable interrupts first! */
\r
238 __disable_interrupt();
\r
240 /* Now interrupts are disabled ulCriticalNesting can be accessed
\r
241 directly. Increment ulCriticalNesting to keep a count of how many times
\r
242 portENTER_CRITICAL() has been called. */
\r
243 ulCriticalNesting++;
\r
245 /*-----------------------------------------------------------*/
\r
247 __arm __interwork void vPortExitCritical( void )
\r
249 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
\r
251 /* Decrement the nesting count as we are leaving a critical section. */
\r
252 ulCriticalNesting--;
\r
254 /* If the nesting level has reached zero then interrupts should be
\r
256 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
\r
258 __enable_interrupt();
\r
262 /*-----------------------------------------------------------*/
\r