2 FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.
\r
5 ***************************************************************************
\r
7 * FreeRTOS tutorial books are available in pdf and paperback. *
\r
8 * Complete, revised, and edited pdf reference manuals are also *
\r
11 * Purchasing FreeRTOS documentation will not only help you, by *
\r
12 * ensuring you get running as quickly as possible and with an *
\r
13 * in-depth knowledge of how to use FreeRTOS, it will also help *
\r
14 * the FreeRTOS project to continue with its mission of providing *
\r
15 * professional grade, cross platform, de facto standard solutions *
\r
16 * for microcontrollers - completely free of charge! *
\r
18 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
\r
20 * Thank you for using FreeRTOS, and thank you for your support! *
\r
22 ***************************************************************************
\r
25 This file is part of the FreeRTOS distribution.
\r
27 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
28 the terms of the GNU General Public License (version 2) as published by the
\r
29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
\r
30 >>>NOTE<<< The modification to the GPL is included to allow you to
\r
31 distribute a combined work that includes FreeRTOS without being obliged to
\r
32 provide the source code for proprietary components outside of the FreeRTOS
\r
33 kernel. FreeRTOS is distributed in the hope that it will be useful, but
\r
34 WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
\r
35 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
36 more details. You should have received a copy of the GNU General Public
\r
37 License and the FreeRTOS license exception along with FreeRTOS; if not it
\r
38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
\r
39 by writing to Richard Barry, contact details for whom are available on the
\r
44 http://www.FreeRTOS.org - Documentation, latest information, license and
\r
47 http://www.SafeRTOS.com - A version that is certified for use in safety
\r
50 http://www.OpenRTOS.com - Commercial support, development, porting,
\r
51 licensing and training services.
\r
54 /*-----------------------------------------------------------
\r
55 * Implementation of functions defined in portable.h for the ST STR75x ARM7
\r
57 *----------------------------------------------------------*/
\r
59 /* Library includes. */
\r
61 #include "75x_eic.h"
\r
63 /* Scheduler includes. */
\r
64 #include "FreeRTOS.h"
\r
67 /* Constants required to setup the initial stack. */
\r
68 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
\r
69 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
\r
71 /* Constants required to handle critical sections. */
\r
72 #define portNO_CRITICAL_NESTING ( ( unsigned long ) 0 )
\r
74 /* Prescale used on the timer clock when calculating the tick period. */
\r
75 #define portPRESCALE 20
\r
78 /*-----------------------------------------------------------*/
\r
80 /* Setup the TB to generate the tick interrupts. */
\r
81 static void prvSetupTimerInterrupt( void );
\r
83 /* ulCriticalNesting will get set to zero when the first task starts. It
\r
84 cannot be initialised to 0 as this will cause interrupts to be enabled
\r
85 during the kernel initialisation process. */
\r
86 unsigned long ulCriticalNesting = ( unsigned long ) 9999;
\r
88 /* Tick interrupt routines for preemptive operation. */
\r
89 __arm void vPortPreemptiveTick( void );
\r
91 /*-----------------------------------------------------------*/
\r
94 * Initialise the stack of a task to look exactly as if a call to
\r
95 * portSAVE_CONTEXT had been called.
\r
97 * See header file for description.
\r
99 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
\r
101 portSTACK_TYPE *pxOriginalTOS;
\r
103 pxOriginalTOS = pxTopOfStack;
\r
105 /* To ensure asserts in tasks.c don't fail, although in this case the assert
\r
106 is not really required. */
\r
109 /* Setup the initial stack of the task. The stack is set exactly as
\r
110 expected by the portRESTORE_CONTEXT() macro. */
\r
112 /* First on the stack is the return address - which in this case is the
\r
113 start of the task. The offset is added to make the return address appear
\r
114 as it would within an IRQ ISR. */
\r
115 *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
\r
118 *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
\r
120 *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
\r
122 *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
\r
124 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
\r
126 *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
\r
128 *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
\r
130 *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
\r
132 *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
\r
134 *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
\r
136 *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
\r
138 *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
\r
140 *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
\r
142 *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
\r
144 *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
\r
147 /* When the task starts is will expect to find the function parameter in
\r
149 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
\r
152 /* The status register is set for system mode, with interrupts enabled. */
\r
153 *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
\r
156 /* Interrupt flags cannot always be stored on the stack and will
\r
157 instead be stored in a variable, which is then saved as part of the
\r
159 *pxTopOfStack = portNO_CRITICAL_NESTING;
\r
161 return pxTopOfStack;
\r
163 /*-----------------------------------------------------------*/
\r
165 portBASE_TYPE xPortStartScheduler( void )
\r
167 extern void vPortStartFirstTask( void );
\r
169 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
171 prvSetupTimerInterrupt();
\r
173 /* Start the first task. */
\r
174 vPortStartFirstTask();
\r
176 /* Should not get here! */
\r
179 /*-----------------------------------------------------------*/
\r
181 void vPortEndScheduler( void )
\r
183 /* It is unlikely that the ARM port will require this function as there
\r
184 is nothing to return to. */
\r
186 /*-----------------------------------------------------------*/
\r
188 __arm void vPortPreemptiveTick( void )
\r
190 /* Increment the tick counter. */
\r
191 vTaskIncrementTick();
\r
193 /* The new tick value might unblock a task. Ensure the highest task that
\r
194 is ready to execute is the task that will execute when the tick ISR
\r
196 #if configUSE_PREEMPTION == 1
\r
197 vTaskSwitchContext();
\r
200 TB_ClearITPendingBit( TB_IT_Update );
\r
202 /*-----------------------------------------------------------*/
\r
204 static void prvSetupTimerInterrupt( void )
\r
206 EIC_IRQInitTypeDef EIC_IRQInitStructure;
\r
207 TB_InitTypeDef TB_InitStructure;
\r
209 /* Setup the EIC for the TB. */
\r
210 EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
\r
211 EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
\r
212 EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
\r
213 EIC_IRQInit(&EIC_IRQInitStructure);
\r
215 /* Setup the TB for the generation of the tick interrupt. */
\r
216 TB_InitStructure.TB_Mode = TB_Mode_Timing;
\r
217 TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
\r
218 TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
\r
219 TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
\r
220 TB_Init(&TB_InitStructure);
\r
222 /* Enable TB Update interrupt */
\r
223 TB_ITConfig(TB_IT_Update, ENABLE);
\r
225 /* Clear TB Update interrupt pending bit */
\r
226 TB_ClearITPendingBit(TB_IT_Update);
\r
231 /*-----------------------------------------------------------*/
\r
233 __arm __interwork void vPortEnterCritical( void )
\r
235 /* Disable interrupts first! */
\r
236 __disable_interrupt();
\r
238 /* Now interrupts are disabled ulCriticalNesting can be accessed
\r
239 directly. Increment ulCriticalNesting to keep a count of how many times
\r
240 portENTER_CRITICAL() has been called. */
\r
241 ulCriticalNesting++;
\r
243 /*-----------------------------------------------------------*/
\r
245 __arm __interwork void vPortExitCritical( void )
\r
247 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
\r
249 /* Decrement the nesting count as we are leaving a critical section. */
\r
250 ulCriticalNesting--;
\r
252 /* If the nesting level has reached zero then interrupts should be
\r
254 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
\r
256 __enable_interrupt();
\r
260 /*-----------------------------------------------------------*/
\r