2 FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.
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4 This file is part of the FreeRTOS distribution.
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6 FreeRTOS is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 ***************************************************************************
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29 * SAVE TIME AND MONEY! Why not get us to quote to get FreeRTOS.org *
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30 * running on your hardware - or even write all or part of your application*
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31 * for you? See http://www.OpenRTOS.com for details. *
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33 ***************************************************************************
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34 ***************************************************************************
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36 Please ensure to read the configuration and relevant port sections of the
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37 online documentation.
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39 http://www.FreeRTOS.org - Documentation, latest information, license and
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42 http://www.SafeRTOS.com - A version that is certified for use in safety
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45 http://www.OpenRTOS.com - Commercial support, development, porting,
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46 licensing and training services.
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49 /*-----------------------------------------------------------
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50 * Implementation of functions defined in portable.h for the ST STR91x ARM9
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52 *----------------------------------------------------------*/
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54 /* Library includes. */
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55 #include "91x_lib.h"
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57 /* Standard includes. */
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61 /* Scheduler includes. */
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62 #include "FreeRTOS.h"
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65 #ifndef configUSE_WATCHDOG_TICK
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66 #error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively.
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69 /* Constants required to setup the initial stack. */
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70 #ifndef _RUN_TASK_IN_ARM_MODE_
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71 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
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73 #define portINITIAL_SPSR ( ( portSTACK_TYPE ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
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76 #define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 4 )
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78 /* Constants required to handle critical sections. */
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79 #define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
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82 #define abs(x) ((x)>0 ? (x) : -(x))
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86 * Toggle a led using the following algorithm:
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87 * if ( GPIO_ReadBit(GPIO9, GPIO_Pin_2) )
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89 * GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
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93 * GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
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97 #define TOGGLE_LED(port,pin) \
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98 if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET ) \
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100 (port)->DR[(pin) <<2] = 0x00; \
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104 (port)->DR[(pin) <<2] = (pin); \
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108 /*-----------------------------------------------------------*/
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110 /* Setup the watchdog to generate the tick interrupts. */
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111 static void prvSetupTimerInterrupt( void );
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113 /* ulCriticalNesting will get set to zero when the first task starts. It
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114 cannot be initialised to 0 as this will cause interrupts to be enabled
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115 during the kernel initialisation process. */
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116 unsigned portLONG ulCriticalNesting = ( unsigned portLONG ) 9999;
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118 /* Tick interrupt routines for cooperative and preemptive operation
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119 respectively. The preemptive version is not defined as __irq as it is called
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120 from an asm wrapper function. */
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121 void WDG_IRQHandler( void );
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123 /* VIC interrupt default handler. */
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124 static void prvDefaultHandler( void );
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126 #if configUSE_WATCHDOG_TICK == 0
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127 /* Used to update the OCR timer register */
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128 static u16 s_nPulseLength;
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131 /*-----------------------------------------------------------*/
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134 * Initialise the stack of a task to look exactly as if a call to
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135 * portSAVE_CONTEXT had been called.
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137 * See header file for description.
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139 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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141 portSTACK_TYPE *pxOriginalTOS;
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143 pxOriginalTOS = pxTopOfStack;
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145 /* Setup the initial stack of the task. The stack is set exactly as
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146 expected by the portRESTORE_CONTEXT() macro. */
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148 /* First on the stack is the return address - which in this case is the
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149 start of the task. The offset is added to make the return address appear
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150 as it would within an IRQ ISR. */
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151 *pxTopOfStack = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE;
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154 *pxTopOfStack = ( portSTACK_TYPE ) 0xaaaaaaaa; /* R14 */
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156 *pxTopOfStack = ( portSTACK_TYPE ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
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158 *pxTopOfStack = ( portSTACK_TYPE ) 0x12121212; /* R12 */
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160 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111; /* R11 */
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162 *pxTopOfStack = ( portSTACK_TYPE ) 0x10101010; /* R10 */
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164 *pxTopOfStack = ( portSTACK_TYPE ) 0x09090909; /* R9 */
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166 *pxTopOfStack = ( portSTACK_TYPE ) 0x08080808; /* R8 */
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168 *pxTopOfStack = ( portSTACK_TYPE ) 0x07070707; /* R7 */
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170 *pxTopOfStack = ( portSTACK_TYPE ) 0x06060606; /* R6 */
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172 *pxTopOfStack = ( portSTACK_TYPE ) 0x05050505; /* R5 */
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174 *pxTopOfStack = ( portSTACK_TYPE ) 0x04040404; /* R4 */
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176 *pxTopOfStack = ( portSTACK_TYPE ) 0x03030303; /* R3 */
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178 *pxTopOfStack = ( portSTACK_TYPE ) 0x02020202; /* R2 */
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180 *pxTopOfStack = ( portSTACK_TYPE ) 0x01010101; /* R1 */
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183 /* When the task starts is will expect to find the function parameter in
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185 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
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188 /* The status register is set for system mode, with interrupts enabled. */
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189 *pxTopOfStack = ( portSTACK_TYPE ) portINITIAL_SPSR;
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192 /* Interrupt flags cannot always be stored on the stack and will
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193 instead be stored in a variable, which is then saved as part of the
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195 *pxTopOfStack = portNO_CRITICAL_NESTING;
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197 return pxTopOfStack;
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199 /*-----------------------------------------------------------*/
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201 portBASE_TYPE xPortStartScheduler( void )
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203 extern void vPortStartFirstTask( void );
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205 /* Start the timer that generates the tick ISR. Interrupts are disabled
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207 prvSetupTimerInterrupt();
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209 /* Start the first task. */
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210 vPortStartFirstTask();
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212 /* Should not get here! */
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215 /*-----------------------------------------------------------*/
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217 void vPortEndScheduler( void )
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219 /* It is unlikely that the ARM port will require this function as there
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220 is nothing to return to. */
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222 /*-----------------------------------------------------------*/
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224 /* This function is called from an asm wrapper, so does not require the __irq
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226 #if configUSE_WATCHDOG_TICK == 1
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228 static void prvFindFactors(u32 n, u16 *a, u32 *b)
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230 /* This function is copied from the ST STR7 library and is
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231 copyright STMicroelectronics. Reproduced with permission. */
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235 long err, err_min=n;
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237 *a = a0 = ((n-1)/65536ul) + 1;
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240 for (; *a <= 256; (*a)++)
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243 err = (long)*a * (long)*b - (long)n;
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244 if (abs(err) > (*a / 2))
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247 err = (long)*a * (long)*b - (long)n;
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249 if (abs(err) < abs(err_min))
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254 if (err == 0) break;
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261 /*-----------------------------------------------------------*/
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263 static void prvSetupTimerInterrupt( void )
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265 WDG_InitTypeDef xWdg;
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266 unsigned portSHORT a;
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267 unsigned portLONG n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
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269 /* Configure the watchdog as a free running timer that generates a
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270 periodic interrupt. */
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272 SCU_APBPeriphClockConfig( __WDG, ENABLE );
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274 WDG_StructInit(&xWdg);
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275 prvFindFactors( n, &a, &b );
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276 xWdg.WDG_Prescaler = a - 1;
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277 xWdg.WDG_Preload = b - 1;
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279 WDG_ITConfig(ENABLE);
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281 /* Configure the VIC for the WDG interrupt. */
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282 VIC_Config( WDG_ITLine, VIC_IRQ, 10 );
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283 VIC_ITCmd( WDG_ITLine, ENABLE );
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285 /* Install the default handlers for both VIC's. */
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286 VIC0->DVAR = ( unsigned portLONG ) prvDefaultHandler;
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287 VIC1->DVAR = ( unsigned portLONG ) prvDefaultHandler;
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291 /*-----------------------------------------------------------*/
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293 void WDG_IRQHandler( void )
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296 /* Increment the tick counter. */
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297 vTaskIncrementTick();
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299 #if configUSE_PREEMPTION == 1
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301 /* The new tick value might unblock a task. Ensure the highest task that
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302 is ready to execute is the task that will execute when the tick ISR
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304 vTaskSwitchContext();
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306 #endif /* configUSE_PREEMPTION. */
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308 /* Clear the interrupt in the watchdog. */
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309 WDG->SR &= ~0x0001;
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315 static void prvFindFactors(u32 n, u8 *a, u16 *b)
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317 /* This function is copied from the ST STR7 library and is
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318 copyright STMicroelectronics. Reproduced with permission. */
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322 long err, err_min=n;
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325 *a = a0 = ((n-1)/256) + 1;
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328 for (; *a <= 256; (*a)++)
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331 err = (long)*a * (long)*b - (long)n;
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332 if (abs(err) > (*a / 2))
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335 err = (long)*a * (long)*b - (long)n;
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337 if (abs(err) < abs(err_min))
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342 if (err == 0) break;
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349 /*-----------------------------------------------------------*/
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351 static void prvSetupTimerInterrupt( void )
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353 unsigned portCHAR a;
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354 unsigned portSHORT b;
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355 unsigned portLONG n = configCPU_PERIPH_HZ / configTICK_RATE_HZ;
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357 TIM_InitTypeDef timer;
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359 SCU_APBPeriphClockConfig( __TIM23, ENABLE );
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361 TIM_StructInit(&timer);
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362 prvFindFactors( n, &a, &b );
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364 timer.TIM_Mode = TIM_OCM_CHANNEL_1;
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365 timer.TIM_OC1_Modes = TIM_TIMING;
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366 timer.TIM_Clock_Source = TIM_CLK_APB;
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367 timer.TIM_Clock_Edge = TIM_CLK_EDGE_RISING;
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368 timer.TIM_Prescaler = a-1;
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369 timer.TIM_Pulse_Level_1 = TIM_HIGH;
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370 timer.TIM_Pulse_Length_1 = s_nPulseLength = b-1;
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372 TIM_Init (TIM2, &timer);
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373 TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE);
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374 /* Configure the VIC for the WDG interrupt. */
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375 VIC_Config( TIM2_ITLine, VIC_IRQ, 10 );
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376 VIC_ITCmd( TIM2_ITLine, ENABLE );
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378 /* Install the default handlers for both VIC's. */
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379 VIC0->DVAR = ( unsigned portLONG ) prvDefaultHandler;
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380 VIC1->DVAR = ( unsigned portLONG ) prvDefaultHandler;
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382 TIM_CounterCmd(TIM2, TIM_CLEAR);
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383 TIM_CounterCmd(TIM2, TIM_START);
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385 /*-----------------------------------------------------------*/
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387 void TIM2_IRQHandler( void )
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389 /* Reset the timer counter to avioid overflow. */
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390 TIM2->OC1R += s_nPulseLength;
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392 /* Increment the tick counter. */
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393 vTaskIncrementTick();
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395 #if configUSE_PREEMPTION == 1
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397 /* The new tick value might unblock a task. Ensure the highest task that
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398 is ready to execute is the task that will execute when the tick ISR
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400 vTaskSwitchContext();
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404 /* Clear the interrupt in the watchdog. */
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405 TIM2->SR &= ~TIM_FLAG_OC1;
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408 #endif /* USE_WATCHDOG_TICK */
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410 /*-----------------------------------------------------------*/
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412 __arm __interwork void vPortEnterCritical( void )
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414 /* Disable interrupts first! */
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415 portDISABLE_INTERRUPTS();
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417 /* Now interrupts are disabled ulCriticalNesting can be accessed
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418 directly. Increment ulCriticalNesting to keep a count of how many times
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419 portENTER_CRITICAL() has been called. */
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420 ulCriticalNesting++;
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422 /*-----------------------------------------------------------*/
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424 __arm __interwork void vPortExitCritical( void )
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426 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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428 /* Decrement the nesting count as we are leaving a critical section. */
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429 ulCriticalNesting--;
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431 /* If the nesting level has reached zero then interrupts should be
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433 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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435 portENABLE_INTERRUPTS();
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439 /*-----------------------------------------------------------*/
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441 static void prvDefaultHandler( void )
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