2 FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 See http://www.FreeRTOS.org for documentation, latest information, license
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28 and contact details. Please ensure to read the configuration and relevant
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29 port sections of the online documentation.
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31 Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
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32 with commercial development and support options.
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33 ***************************************************************************
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37 /*-----------------------------------------------------------
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38 * Components that can be compiled to either ARM or THUMB mode are
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39 * contained in port.c The ISR routines, which can only be compiled
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40 * to ARM mode, are contained in this file.
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41 *----------------------------------------------------------*/
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43 /* This file must always be compiled to ARM mode as it contains ISR
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47 /* Scheduler includes. */
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48 #include "FreeRTOS.h"
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51 /* Constants required to handle interrupts. */
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52 #define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )
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53 #define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
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55 /*-----------------------------------------------------------*/
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57 /* The code generated by the Keil compiler does not maintain separate
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58 stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
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59 use the stack as per other ports. Instead a variable is used to keep
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60 track of the critical section nesting. This variable has to be stored
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61 as part of the task context and must be initialised to a non zero value. */
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63 #define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
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64 volatile unsigned portLONG ulCriticalNesting = 9999UL;
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66 /*-----------------------------------------------------------*/
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68 /* ISR to handle manual context switches (from a call to taskYIELD()). */
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69 void vPortYieldProcessor( void );
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72 * The scheduler can only be started from ARM mode, hence the inclusion of this
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75 void vPortISRStartFirstTask( void );
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77 /*-----------------------------------------------------------*/
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79 void vPortISRStartFirstTask( void )
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81 /* Simply start the scheduler. This is included here as it can only be
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82 called from ARM mode. */
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83 portRESTORE_CONTEXT();
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85 /*-----------------------------------------------------------*/
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88 * Interrupt service routine for the SWI interrupt. The vector table is
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89 * configured within startup.s.
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91 * vPortYieldProcessor() is used to manually force a context switch. The
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92 * SWI interrupt is generated by a call to taskYIELD() or portYIELD().
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94 void vPortYieldProcessor( void ) __task
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96 /* Within an IRQ ISR the link register has an offset from the true return
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97 address, but an SWI ISR does not. Add the offset manually so the same
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98 ISR return code can be used in both cases. */
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99 __asm{ ADD LR, LR, #4 };
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101 /* Perform the context switch. */
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102 portSAVE_CONTEXT();
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103 vTaskSwitchContext();
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104 portRESTORE_CONTEXT();
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106 /*-----------------------------------------------------------*/
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109 * The ISR used for the scheduler tick depends on whether the cooperative or
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110 * the preemptive scheduler is being used.
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113 #if configUSE_PREEMPTION == 0
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116 * The cooperative scheduler requires a normal IRQ service routine to
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117 * simply increment the system tick.
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119 void vNonPreemptiveTick( void );
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120 void vNonPreemptiveTick( void ) __irq
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122 /* Increment the tick count - this may make a delaying task ready
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123 to run - but a context switch is not performed. */
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124 vTaskIncrementTick();
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126 /* Ready for the next interrupt. */
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127 T0IR = portTIMER_MATCH_ISR_BIT;
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128 VICVectAddr = portCLEAR_VIC_INTERRUPT;
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134 * The preemptive scheduler ISR is defined as "naked" as the full context
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135 * is saved on entry as part of the context switch.
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137 void vPreemptiveTick( void );
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138 void vPreemptiveTick( void ) __task
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140 /* Save the context of the current task. */
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141 portSAVE_CONTEXT();
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143 /* Increment the tick count - this may make a delayed task ready to
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145 vTaskIncrementTick();
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147 /* Find the highest priority task that is ready to run. */
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148 vTaskSwitchContext();
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150 /* Ready for the next interrupt. */
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151 T0IR = portTIMER_MATCH_ISR_BIT;
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152 VICVectAddr = portCLEAR_VIC_INTERRUPT;
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154 /* Restore the context of the highest priority task that is ready to
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156 portRESTORE_CONTEXT();
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159 /*-----------------------------------------------------------*/
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162 * The interrupt management utilities can only be called from ARM mode. When
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163 * KEIL_THUMB_INTERWORK is defined the utilities are defined as functions here
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164 * to ensure a switch to ARM mode. When KEIL_THUMB_INTERWORK is not defined
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165 * then the utilities are defined as macros in portmacro.h - as per other
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168 #ifdef KEIL_THUMB_INTERWORK
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170 void vPortDisableInterruptsFromThumb( void ) __task;
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171 void vPortEnableInterruptsFromThumb( void ) __task;
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173 void vPortDisableInterruptsFromThumb( void ) __task
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175 __asm{ STMDB SP!, {R0} }; /* Push R0. */
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176 __asm{ MRS R0, CPSR }; /* Get CPSR. */
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177 __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */
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178 __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */
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179 __asm{ LDMIA SP!, {R0} }; /* Pop R0. */
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180 __asm{ BX R14 }; /* Return back to thumb. */
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183 void vPortEnableInterruptsFromThumb( void ) __task
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185 __asm{ STMDB SP!, {R0} }; /* Push R0. */
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186 __asm{ MRS R0, CPSR }; /* Get CPSR. */
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187 __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */
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188 __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */
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189 __asm{ LDMIA SP!, {R0} }; /* Pop R0. */
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190 __asm{ BX R14 }; /* Return back to thumb. */
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193 #endif /* KEIL_THUMB_INTERWORK */
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197 /* The code generated by the Keil compiler does not maintain separate
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198 stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
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199 use the stack as per other ports. Instead a variable is used to keep
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200 track of the critical section nesting. This necessitates the use of a
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201 function in place of the macro. */
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203 void vPortEnterCritical( void )
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205 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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206 __asm{ STMDB SP!, {R0} }; /* Push R0. */
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207 __asm{ MRS R0, CPSR }; /* Get CPSR. */
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208 __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */
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209 __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */
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210 __asm{ LDMIA SP!, {R0} }; /* Pop R0. */
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212 /* Now interrupts are disabled ulCriticalNesting can be accessed
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213 directly. Increment ulCriticalNesting to keep a count of how many times
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214 portENTER_CRITICAL() has been called. */
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215 ulCriticalNesting++;
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218 void vPortExitCritical( void )
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220 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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222 /* Decrement the nesting count as we are leaving a critical section. */
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223 ulCriticalNesting--;
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225 /* If the nesting level has reached zero then interrupts should be
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227 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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229 /* Enable interrupts as per portEXIT_CRITICAL(). */
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230 __asm{ STMDB SP!, {R0} }; /* Push R0. */
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231 __asm{ MRS R0, CPSR }; /* Get CPSR. */
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232 __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */
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233 __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */
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234 __asm{ LDMIA SP!, {R0} }; /* Pop R0. */
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