2 FreeRTOS.org V5.0.2 - Copyright (C) 2003-2008 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 ***************************************************************************
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29 * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
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30 * and even write all or part of your application on your behalf. *
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31 * See http://www.OpenRTOS.com for details of the services we provide to *
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32 * expedite your project. *
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34 ***************************************************************************
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35 ***************************************************************************
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37 Please ensure to read the configuration and relevant port sections of the
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38 online documentation.
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40 http://www.FreeRTOS.org - Documentation, latest information, license and
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43 http://www.SafeRTOS.com - A version that is certified for use in safety
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46 http://www.OpenRTOS.com - Commercial support, development, porting,
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47 licensing and training services.
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51 /*-----------------------------------------------------------
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52 * Components that can be compiled to either ARM or THUMB mode are
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53 * contained in port.c The ISR routines, which can only be compiled
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54 * to ARM mode, are contained in this file.
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55 *----------------------------------------------------------*/
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57 /* This file must always be compiled to ARM mode as it contains ISR
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61 /* Scheduler includes. */
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62 #include "FreeRTOS.h"
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65 /* Constants required to handle interrupts. */
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66 #define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )
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67 #define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
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69 /*-----------------------------------------------------------*/
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71 /* The code generated by the Keil compiler does not maintain separate
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72 stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
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73 use the stack as per other ports. Instead a variable is used to keep
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74 track of the critical section nesting. This variable has to be stored
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75 as part of the task context and must be initialised to a non zero value. */
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77 #define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
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78 volatile unsigned portLONG ulCriticalNesting = 9999UL;
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80 /*-----------------------------------------------------------*/
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82 /* ISR to handle manual context switches (from a call to taskYIELD()). */
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83 void vPortYieldProcessor( void );
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86 * The scheduler can only be started from ARM mode, hence the inclusion of this
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89 void vPortISRStartFirstTask( void );
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91 /*-----------------------------------------------------------*/
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93 void vPortISRStartFirstTask( void )
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95 /* Simply start the scheduler. This is included here as it can only be
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96 called from ARM mode. */
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97 portRESTORE_CONTEXT();
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99 /*-----------------------------------------------------------*/
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102 * Interrupt service routine for the SWI interrupt. The vector table is
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103 * configured within startup.s.
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105 * vPortYieldProcessor() is used to manually force a context switch. The
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106 * SWI interrupt is generated by a call to taskYIELD() or portYIELD().
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108 void vPortYieldProcessor( void ) __task
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110 /* Within an IRQ ISR the link register has an offset from the true return
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111 address, but an SWI ISR does not. Add the offset manually so the same
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112 ISR return code can be used in both cases. */
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113 __asm{ ADD LR, LR, #4 };
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115 /* Perform the context switch. */
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116 portSAVE_CONTEXT();
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117 vTaskSwitchContext();
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118 portRESTORE_CONTEXT();
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120 /*-----------------------------------------------------------*/
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123 * The ISR used for the scheduler tick depends on whether the cooperative or
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124 * the preemptive scheduler is being used.
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127 #if configUSE_PREEMPTION == 0
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130 * The cooperative scheduler requires a normal IRQ service routine to
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131 * simply increment the system tick.
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133 void vNonPreemptiveTick( void );
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134 void vNonPreemptiveTick( void ) __irq
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136 /* Increment the tick count - this may make a delaying task ready
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137 to run - but a context switch is not performed. */
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138 vTaskIncrementTick();
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140 /* Ready for the next interrupt. */
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141 T0IR = portTIMER_MATCH_ISR_BIT;
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142 VICVectAddr = portCLEAR_VIC_INTERRUPT;
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148 * The preemptive scheduler ISR is defined as "naked" as the full context
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149 * is saved on entry as part of the context switch.
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151 void vPreemptiveTick( void );
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152 void vPreemptiveTick( void ) __task
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154 /* Save the context of the current task. */
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155 portSAVE_CONTEXT();
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157 /* Increment the tick count - this may make a delayed task ready to
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159 vTaskIncrementTick();
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161 /* Find the highest priority task that is ready to run. */
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162 vTaskSwitchContext();
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164 /* Ready for the next interrupt. */
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165 T0IR = portTIMER_MATCH_ISR_BIT;
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166 VICVectAddr = portCLEAR_VIC_INTERRUPT;
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168 /* Restore the context of the highest priority task that is ready to
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170 portRESTORE_CONTEXT();
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173 /*-----------------------------------------------------------*/
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176 * The interrupt management utilities can only be called from ARM mode. When
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177 * KEIL_THUMB_INTERWORK is defined the utilities are defined as functions here
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178 * to ensure a switch to ARM mode. When KEIL_THUMB_INTERWORK is not defined
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179 * then the utilities are defined as macros in portmacro.h - as per other
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182 #ifdef KEIL_THUMB_INTERWORK
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184 void vPortDisableInterruptsFromThumb( void ) __task;
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185 void vPortEnableInterruptsFromThumb( void ) __task;
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187 void vPortDisableInterruptsFromThumb( void ) __task
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189 __asm{ STMDB SP!, {R0} }; /* Push R0. */
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190 __asm{ MRS R0, CPSR }; /* Get CPSR. */
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191 __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */
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192 __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */
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193 __asm{ LDMIA SP!, {R0} }; /* Pop R0. */
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194 __asm{ BX R14 }; /* Return back to thumb. */
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197 void vPortEnableInterruptsFromThumb( void ) __task
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199 __asm{ STMDB SP!, {R0} }; /* Push R0. */
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200 __asm{ MRS R0, CPSR }; /* Get CPSR. */
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201 __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */
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202 __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */
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203 __asm{ LDMIA SP!, {R0} }; /* Pop R0. */
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204 __asm{ BX R14 }; /* Return back to thumb. */
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207 #endif /* KEIL_THUMB_INTERWORK */
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211 /* The code generated by the Keil compiler does not maintain separate
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212 stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
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213 use the stack as per other ports. Instead a variable is used to keep
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214 track of the critical section nesting. This necessitates the use of a
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215 function in place of the macro. */
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217 void vPortEnterCritical( void )
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219 /* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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220 __asm{ STMDB SP!, {R0} }; /* Push R0. */
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221 __asm{ MRS R0, CPSR }; /* Get CPSR. */
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222 __asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */
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223 __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */
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224 __asm{ LDMIA SP!, {R0} }; /* Pop R0. */
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226 /* Now interrupts are disabled ulCriticalNesting can be accessed
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227 directly. Increment ulCriticalNesting to keep a count of how many times
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228 portENTER_CRITICAL() has been called. */
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229 ulCriticalNesting++;
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232 void vPortExitCritical( void )
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234 if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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236 /* Decrement the nesting count as we are leaving a critical section. */
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237 ulCriticalNesting--;
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239 /* If the nesting level has reached zero then interrupts should be
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241 if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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243 /* Enable interrupts as per portEXIT_CRITICAL(). */
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244 __asm{ STMDB SP!, {R0} }; /* Push R0. */
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245 __asm{ MRS R0, CPSR }; /* Get CPSR. */
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246 __asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */
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247 __asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */
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248 __asm{ LDMIA SP!, {R0} }; /* Pop R0. */
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