2 FreeRTOS.org V4.3.0 - Copyright (C) 2003-2007 Richard Barry.
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4 This file is part of the FreeRTOS.org distribution.
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6 FreeRTOS.org is free software; you can redistribute it and/or modify
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7 it under the terms of the GNU General Public License as published by
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8 the Free Software Foundation; either version 2 of the License, or
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9 (at your option) any later version.
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11 FreeRTOS.org is distributed in the hope that it will be useful,
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12 but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 GNU General Public License for more details.
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16 You should have received a copy of the GNU General Public License
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17 along with FreeRTOS.org; if not, write to the Free Software
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18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 A special exception to the GPL can be applied should you wish to distribute
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21 a combined work that includes FreeRTOS.org, without being obliged to provide
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22 the source code for any proprietary components. See the licensing section
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23 of http://www.FreeRTOS.org for full details of how and when the exception
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26 ***************************************************************************
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27 See http://www.FreeRTOS.org for documentation, latest information, license
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28 and contact details. Please ensure to read the configuration and relevant
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29 port sections of the online documentation.
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31 Also see http://www.SafeRTOS.com for an IEC 61508 compliant version along
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32 with commercial development and support options.
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33 ***************************************************************************
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37 Changes between V1.2.4 and V1.2.5
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39 + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
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40 interrupt flag setting. Using the two bits defined within
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41 portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
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42 before the test was performed.
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46 + Set the interrupt vector address to 0x08. Previously it was at the
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47 incorrect address for compatibility mode of 0x18.
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51 + PCLATU and PCLATH are now saved as part of the context. This allows
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52 function pointers to be used within tasks. Thanks to Javier Espeche
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53 for the enhancement.
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57 + TABLAT is now saved as part of the task context.
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61 + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
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62 value and does not write to the register.
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65 /* Scheduler include files. */
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66 #include "FreeRTOS.h"
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69 /* MPLAB library include file. */
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72 /*-----------------------------------------------------------
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73 * Implementation of functions defined in portable.h for the PIC port.
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74 *----------------------------------------------------------*/
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76 /* Hardware setup for tick. */
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77 #define portTIMER_FOSC_SCALE ( ( unsigned portLONG ) 4 )
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79 /* Initial interrupt enable state for newly created tasks. This value is
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80 copied into INTCON when a task switches in for the first time. */
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81 #define portINITAL_INTERRUPT_STATE 0xc0
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83 /* Just the bit within INTCON for the global interrupt flag. */
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84 #define portGLOBAL_INTERRUPT_FLAG 0x80
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86 /* Constant used for context switch macro when we require the interrupt
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87 enable state to be unchanged when the interrupted task is switched back in. */
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88 #define portINTERRUPTS_UNCHANGED 0x00
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90 /* Some memory areas get saved as part of the task context. These memory
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91 area's get used by the compiler for temporary storage, especially when
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92 performing mathematical operations, or when using 32bit data types. This
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93 constant defines the size of memory area which must be saved. */
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94 #define portCOMPILER_MANAGED_MEMORY_SIZE ( ( unsigned portCHAR ) 0x13 )
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96 /* We require the address of the pxCurrentTCB variable, but don't want to know
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97 any details of its type. */
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98 typedef void tskTCB;
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99 extern volatile tskTCB * volatile pxCurrentTCB;
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101 /* IO port constants. */
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102 #define portBIT_SET ( ( unsigned portCHAR ) 1 )
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103 #define portBIT_CLEAR ( ( unsigned portCHAR ) 0 )
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106 * The serial port ISR's are defined in serial.c, but are called from portable
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107 * as they use the same vector as the tick ISR.
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109 void vSerialTxISR( void );
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110 void vSerialRxISR( void );
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113 * Perform hardware setup to enable ticks.
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115 static void prvSetupTimerInterrupt( void );
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118 * ISR to maintain the tick, and perform tick context switches if the
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119 * preemptive scheduler is being used.
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121 static void prvTickISR( void );
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124 * ISR placed on the low priority vector. This calls the appropriate ISR for
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125 * the actual interrupt.
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127 static void prvLowInterrupt( void );
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130 * Macro that pushes all the registers that make up the context of a task onto
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131 * the stack, then saves the new top of stack into the TCB.
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133 * If this is called from an ISR then the interrupt enable bits must have been
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134 * set for the ISR to ever get called. Therefore we want to save the INTCON
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135 * register with the enable bits forced to be set - and ucForcedInterruptFlags
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136 * must contain these bit settings. This means the interrupts will again be
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137 * enabled when the interrupted task is switched back in.
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139 * If this is called from a manual context switch (i.e. from a call to yield),
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140 * then we want to save the INTCON so it is restored with its current state,
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141 * and ucForcedInterruptFlags must be 0. This allows a yield from within
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142 * a critical section.
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144 * The compiler uses some locations at the bottom of the memory for temporary
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145 * storage during math and other computations. This is especially true if
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146 * 32bit data types are utilised (as they are by the scheduler). The .tmpdata
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147 * and MATH_DATA sections have to be stored in there entirety as part of a task
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148 * context. This macro stores from data address 0x00 to
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149 * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
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150 * applications but you should check the map file for your project to ensure
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151 * this is sufficient for your needs. It is not clear whether this size is
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152 * fixed for all compilations or has the potential to be program specific.
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154 #define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
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157 /* Save the status and WREG registers first, as these will get modified \
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158 by the operations below. */ \
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159 MOVFF WREG, PREINC1 \
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160 MOVFF STATUS, PREINC1 \
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161 /* Save the INTCON register with the appropriate bits forced if \
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162 necessary - as described above. */ \
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163 MOVFF INTCON, WREG \
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164 IORLW ucForcedInterruptFlags \
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165 MOVFF WREG, PREINC1 \
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168 portDISABLE_INTERRUPTS(); \
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171 /* Store the necessary registers to the stack. */ \
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172 MOVFF BSR, PREINC1 \
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173 MOVFF FSR2L, PREINC1 \
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174 MOVFF FSR2H, PREINC1 \
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175 MOVFF FSR0L, PREINC1 \
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176 MOVFF FSR0H, PREINC1 \
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177 MOVFF TABLAT, PREINC1 \
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178 MOVFF TBLPTRU, PREINC1 \
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179 MOVFF TBLPTRH, PREINC1 \
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180 MOVFF TBLPTRL, PREINC1 \
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181 MOVFF PRODH, PREINC1 \
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182 MOVFF PRODL, PREINC1 \
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183 MOVFF PCLATU, PREINC1 \
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184 MOVFF PCLATH, PREINC1 \
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185 /* Store the .tempdata and MATH_DATA areas as described above. */ \
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188 MOVFF POSTINC0, PREINC1 \
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189 MOVFF POSTINC0, PREINC1 \
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190 MOVFF POSTINC0, PREINC1 \
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191 MOVFF POSTINC0, PREINC1 \
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192 MOVFF POSTINC0, PREINC1 \
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193 MOVFF POSTINC0, PREINC1 \
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194 MOVFF POSTINC0, PREINC1 \
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195 MOVFF POSTINC0, PREINC1 \
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196 MOVFF POSTINC0, PREINC1 \
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197 MOVFF POSTINC0, PREINC1 \
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198 MOVFF POSTINC0, PREINC1 \
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199 MOVFF POSTINC0, PREINC1 \
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200 MOVFF POSTINC0, PREINC1 \
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201 MOVFF POSTINC0, PREINC1 \
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202 MOVFF POSTINC0, PREINC1 \
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203 MOVFF POSTINC0, PREINC1 \
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204 MOVFF POSTINC0, PREINC1 \
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205 MOVFF POSTINC0, PREINC1 \
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206 MOVFF POSTINC0, PREINC1 \
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207 MOVFF INDF0, PREINC1 \
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208 MOVFF FSR0L, PREINC1 \
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209 MOVFF FSR0H, PREINC1 \
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210 /* Store the hardware stack pointer in a temp register before we \
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212 MOVFF STKPTR, FSR0L \
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215 /* Store each address from the hardware stack. */ \
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216 while( STKPTR > ( unsigned portCHAR ) 0 ) \
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219 MOVFF TOSL, PREINC1 \
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220 MOVFF TOSH, PREINC1 \
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221 MOVFF TOSU, PREINC1 \
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227 /* Store the number of addresses on the hardware stack (from the \
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228 temporary register). */ \
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229 MOVFF FSR0L, PREINC1 \
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230 MOVF PREINC1, 1, 0 \
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233 /* Save the new top of the software stack in the TCB. */ \
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235 MOVFF pxCurrentTCB, FSR0L \
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236 MOVFF pxCurrentTCB + 1, FSR0H \
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237 MOVFF FSR1L, POSTINC0 \
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238 MOVFF FSR1H, POSTINC0 \
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241 /*-----------------------------------------------------------*/
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244 * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
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247 #define portRESTORE_CONTEXT() \
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250 /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
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251 MOVFF pxCurrentTCB, FSR0L \
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252 MOVFF pxCurrentTCB + 1, FSR0H \
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254 /* De-reference FSR0 to set the address it holds into FSR1. \
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255 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
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256 MOVFF POSTINC0, FSR1L \
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257 MOVFF POSTINC0, FSR1H \
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259 /* How many return addresses are there on the hardware stack? Discard \
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260 the first byte as we are pointing to the next free space. */ \
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261 MOVFF POSTDEC1, FSR0L \
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262 MOVFF POSTDEC1, FSR0L \
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265 /* Fill the hardware stack from our software stack. */ \
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268 while( STKPTR < FSR0L ) \
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272 MOVF POSTDEC1, 0, 0 \
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274 MOVF POSTDEC1, 0, 0 \
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276 MOVF POSTDEC1, 0, 0 \
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282 /* Restore the .tmpdata and MATH_DATA memory. */ \
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283 MOVFF POSTDEC1, FSR0H \
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284 MOVFF POSTDEC1, FSR0L \
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285 MOVFF POSTDEC1, POSTDEC0 \
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286 MOVFF POSTDEC1, POSTDEC0 \
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287 MOVFF POSTDEC1, POSTDEC0 \
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288 MOVFF POSTDEC1, POSTDEC0 \
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289 MOVFF POSTDEC1, POSTDEC0 \
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290 MOVFF POSTDEC1, POSTDEC0 \
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291 MOVFF POSTDEC1, POSTDEC0 \
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292 MOVFF POSTDEC1, POSTDEC0 \
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293 MOVFF POSTDEC1, POSTDEC0 \
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294 MOVFF POSTDEC1, POSTDEC0 \
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295 MOVFF POSTDEC1, POSTDEC0 \
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296 MOVFF POSTDEC1, POSTDEC0 \
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297 MOVFF POSTDEC1, POSTDEC0 \
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298 MOVFF POSTDEC1, POSTDEC0 \
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299 MOVFF POSTDEC1, POSTDEC0 \
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300 MOVFF POSTDEC1, POSTDEC0 \
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301 MOVFF POSTDEC1, POSTDEC0 \
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302 MOVFF POSTDEC1, POSTDEC0 \
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303 MOVFF POSTDEC1, POSTDEC0 \
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304 MOVFF POSTDEC1, INDF0 \
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305 /* Restore the other registers forming the tasks context. */ \
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306 MOVFF POSTDEC1, PCLATH \
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307 MOVFF POSTDEC1, PCLATU \
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308 MOVFF POSTDEC1, PRODL \
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309 MOVFF POSTDEC1, PRODH \
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310 MOVFF POSTDEC1, TBLPTRL \
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311 MOVFF POSTDEC1, TBLPTRH \
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312 MOVFF POSTDEC1, TBLPTRU \
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313 MOVFF POSTDEC1, TABLAT \
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314 MOVFF POSTDEC1, FSR0H \
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315 MOVFF POSTDEC1, FSR0L \
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316 MOVFF POSTDEC1, FSR2H \
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317 MOVFF POSTDEC1, FSR2L \
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318 MOVFF POSTDEC1, BSR \
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319 /* The next byte is the INTCON register. Read this into WREG as some \
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320 manipulation is required. */ \
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321 MOVFF POSTDEC1, WREG \
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324 /* From the INTCON register, only the interrupt enable bits form part \
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325 of the tasks context. It is perfectly legitimate for another task to \
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326 have modified any other bits. We therefore only restore the top two bits. \
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328 if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
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331 MOVFF POSTDEC1, STATUS \
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332 MOVFF POSTDEC1, WREG \
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333 /* Return enabling interrupts. */ \
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340 MOVFF POSTDEC1, STATUS \
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341 MOVFF POSTDEC1, WREG \
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342 /* Return without effecting interrupts. The context may have \
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343 been saved from a critical region. */ \
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348 /*-----------------------------------------------------------*/
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351 * See header file for description.
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353 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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355 unsigned portLONG ulAddress;
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356 unsigned portCHAR ucBlock;
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358 /* Place a few bytes of known values on the bottom of the stack.
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359 This is just useful for debugging. */
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361 *pxTopOfStack = 0x11;
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363 *pxTopOfStack = 0x22;
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365 *pxTopOfStack = 0x33;
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369 /* Simulate how the stack would look after a call to vPortYield() generated
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372 First store the function parameters. This is where the task will expect to
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373 find them when it starts running. */
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374 ulAddress = ( unsigned portLONG ) pvParameters;
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375 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );
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379 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );
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382 /* Next we just leave a space. When a context is saved the stack pointer
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383 is incremented before it is used so as not to corrupt whatever the stack
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384 pointer is actually pointing to. This is especially necessary during
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385 function epilogue code generated by the compiler. */
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386 *pxTopOfStack = 0x44;
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389 /* Next are all the registers that form part of the task context. */
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391 *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* WREG. */
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394 *pxTopOfStack = ( portSTACK_TYPE ) 0xcc; /* Status. */
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397 /* INTCON is saved with interrupts enabled. */
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398 *pxTopOfStack = ( portSTACK_TYPE ) portINITAL_INTERRUPT_STATE; /* INTCON */
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401 *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* BSR. */
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404 *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* FSR2L. */
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407 *pxTopOfStack = ( portSTACK_TYPE ) 0x33; /* FSR2H. */
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410 *pxTopOfStack = ( portSTACK_TYPE ) 0x44; /* FSR0L. */
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413 *pxTopOfStack = ( portSTACK_TYPE ) 0x55; /* FSR0H. */
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416 *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* TABLAT. */
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419 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */
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422 *pxTopOfStack = ( portSTACK_TYPE ) 0x88; /* TBLPTRUH. */
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425 *pxTopOfStack = ( portSTACK_TYPE ) 0x99; /* TBLPTRUL. */
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428 *pxTopOfStack = ( portSTACK_TYPE ) 0xaa; /* PRODH. */
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431 *pxTopOfStack = ( portSTACK_TYPE ) 0xbb; /* PRODL. */
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434 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATU. */
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437 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATH. */
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440 /* Next the .tmpdata and MATH_DATA sections. */
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441 for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
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443 *pxTopOfStack = ( portSTACK_TYPE ) ucBlock;
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447 /* Store the top of the global data section. */
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448 *pxTopOfStack = ( portSTACK_TYPE ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
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451 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* High. */
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454 /* The only function return address so far is the address of the
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456 ulAddress = ( unsigned portLONG ) pxCode;
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459 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );
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464 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );
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468 /* TOS even higher. */
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469 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );
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472 /* Store the number of return addresses on the hardware stack - so far only
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473 the address of the task entry point. */
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474 *pxTopOfStack = ( portSTACK_TYPE ) 1;
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477 return pxTopOfStack;
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479 /*-----------------------------------------------------------*/
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481 portBASE_TYPE xPortStartScheduler( void )
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483 /* In this port we ignore the parameter and use the configUSE_PREEMPTION
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484 definition instead. */
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486 /* Setup a timer for the tick ISR is using the preemptive scheduler. */
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487 prvSetupTimerInterrupt();
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489 /* Restore the context of the first task to run. */
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490 portRESTORE_CONTEXT();
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492 /* Should not get here. Use the function name to stop compiler warnings. */
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493 ( void ) prvLowInterrupt;
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494 ( void ) prvTickISR;
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498 /*-----------------------------------------------------------*/
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500 void vPortEndScheduler( void )
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502 /* It is unlikely that the scheduler for the PIC port will get stopped
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503 once running. If required disable the tick interrupt here, then return
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504 to xPortStartScheduler(). */
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506 /*-----------------------------------------------------------*/
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509 * Manual context switch. This is similar to the tick context switch,
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510 * but does not increment the tick count. It must be identical to the
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511 * tick context switch in how it stores the stack of a task.
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513 void vPortYield( void )
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515 /* This can get called with interrupts either enabled or disabled. We
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516 will save the INTCON register with the interrupt enable bits unmodified. */
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517 portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
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519 /* Switch to the highest priority task that is ready to run. */
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520 vTaskSwitchContext();
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522 /* Start executing the task we have just switched to. */
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523 portRESTORE_CONTEXT();
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525 /*-----------------------------------------------------------*/
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528 * Vector for ISR. Nothing here must alter any registers!
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530 #pragma code high_vector=0x08
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531 static void prvLowInterrupt( void )
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533 /* Was the interrupt the tick? */
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534 if( PIR1bits.CCP1IF )
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541 /* Was the interrupt a byte being received? */
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542 if( PIR1bits.RCIF )
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549 /* Was the interrupt the Tx register becoming empty? */
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550 if( PIR1bits.TXIF )
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552 if( PIE1bits.TXIE )
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562 /*-----------------------------------------------------------*/
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565 * ISR for the tick.
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566 * This increments the tick count and, if using the preemptive scheduler,
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567 * performs a context switch. This must be identical to the manual
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568 * context switch in how it stores the context of a task.
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570 static void prvTickISR( void )
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572 /* Interrupts must have been enabled for the ISR to fire, so we have to
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573 save the context with interrupts enabled. */
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574 portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
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575 PIR1bits.CCP1IF = 0;
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577 /* Maintain the tick count. */
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578 vTaskIncrementTick();
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580 #if configUSE_PREEMPTION == 1
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582 /* Switch to the highest priority task that is ready to run. */
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583 vTaskSwitchContext();
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587 portRESTORE_CONTEXT();
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589 /*-----------------------------------------------------------*/
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592 * Setup a timer for a regular tick.
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594 static void prvSetupTimerInterrupt( void )
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596 const unsigned portLONG ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
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597 unsigned portLONG ulCompareValue;
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598 unsigned portCHAR ucByte;
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600 /* Interrupts are disabled when this function is called.
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602 Setup CCP1 to provide the tick interrupt using a compare match on timer
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605 Clear the time count then setup timer. */
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606 TMR1H = ( unsigned portCHAR ) 0x00;
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607 TMR1L = ( unsigned portCHAR ) 0x00;
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609 /* Set the compare match value. */
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610 ulCompareValue = ulConstCompareValue;
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611 CCPR1L = ( unsigned portCHAR ) ( ulCompareValue & ( unsigned portLONG ) 0xff );
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612 ulCompareValue >>= ( unsigned portLONG ) 8;
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613 CCPR1H = ( unsigned portCHAR ) ( ulCompareValue & ( unsigned portLONG ) 0xff );
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615 CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
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616 CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
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617 CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
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618 CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
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619 PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
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621 /* We are only going to use the global interrupt bit, so set the peripheral
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623 INTCONbits.GIEL = portBIT_SET;
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625 /* Provided library function for setting up the timer that will produce the
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627 OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
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