2 FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.
\r
4 This file is part of the FreeRTOS.org distribution.
\r
6 FreeRTOS.org is free software; you can redistribute it and/or modify
\r
7 it under the terms of the GNU General Public License as published by
\r
8 the Free Software Foundation; either version 2 of the License, or
\r
9 (at your option) any later version.
\r
11 FreeRTOS.org is distributed in the hope that it will be useful,
\r
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
\r
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
\r
14 GNU General Public License for more details.
\r
16 You should have received a copy of the GNU General Public License
\r
17 along with FreeRTOS.org; if not, write to the Free Software
\r
18 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
\r
20 A special exception to the GPL can be applied should you wish to distribute
\r
21 a combined work that includes FreeRTOS.org, without being obliged to provide
\r
22 the source code for any proprietary components. See the licensing section
\r
23 of http://www.FreeRTOS.org for full details of how and when the exception
\r
26 ***************************************************************************
\r
27 ***************************************************************************
\r
29 * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
\r
30 * and even write all or part of your application on your behalf. *
\r
31 * See http://www.OpenRTOS.com for details of the services we provide to *
\r
32 * expedite your project. *
\r
34 ***************************************************************************
\r
35 ***************************************************************************
\r
37 Please ensure to read the configuration and relevant port sections of the
\r
38 online documentation.
\r
40 http://www.FreeRTOS.org - Documentation, latest information, license and
\r
43 http://www.SafeRTOS.com - A version that is certified for use in safety
\r
46 http://www.OpenRTOS.com - Commercial support, development, porting,
\r
47 licensing and training services.
\r
51 Changes between V1.2.4 and V1.2.5
\r
53 + Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
\r
54 interrupt flag setting. Using the two bits defined within
\r
55 portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
\r
56 before the test was performed.
\r
60 + Set the interrupt vector address to 0x08. Previously it was at the
\r
61 incorrect address for compatibility mode of 0x18.
\r
65 + PCLATU and PCLATH are now saved as part of the context. This allows
\r
66 function pointers to be used within tasks. Thanks to Javier Espeche
\r
67 for the enhancement.
\r
71 + TABLAT is now saved as part of the task context.
\r
75 + TBLPTRU is now initialised to zero as the MPLAB compiler expects this
\r
76 value and does not write to the register.
\r
79 /* Scheduler include files. */
\r
80 #include "FreeRTOS.h"
\r
83 /* MPLAB library include file. */
\r
86 /*-----------------------------------------------------------
\r
87 * Implementation of functions defined in portable.h for the PIC port.
\r
88 *----------------------------------------------------------*/
\r
90 /* Hardware setup for tick. */
\r
91 #define portTIMER_FOSC_SCALE ( ( unsigned portLONG ) 4 )
\r
93 /* Initial interrupt enable state for newly created tasks. This value is
\r
94 copied into INTCON when a task switches in for the first time. */
\r
95 #define portINITAL_INTERRUPT_STATE 0xc0
\r
97 /* Just the bit within INTCON for the global interrupt flag. */
\r
98 #define portGLOBAL_INTERRUPT_FLAG 0x80
\r
100 /* Constant used for context switch macro when we require the interrupt
\r
101 enable state to be unchanged when the interrupted task is switched back in. */
\r
102 #define portINTERRUPTS_UNCHANGED 0x00
\r
104 /* Some memory areas get saved as part of the task context. These memory
\r
105 area's get used by the compiler for temporary storage, especially when
\r
106 performing mathematical operations, or when using 32bit data types. This
\r
107 constant defines the size of memory area which must be saved. */
\r
108 #define portCOMPILER_MANAGED_MEMORY_SIZE ( ( unsigned portCHAR ) 0x13 )
\r
110 /* We require the address of the pxCurrentTCB variable, but don't want to know
\r
111 any details of its type. */
\r
112 typedef void tskTCB;
\r
113 extern volatile tskTCB * volatile pxCurrentTCB;
\r
115 /* IO port constants. */
\r
116 #define portBIT_SET ( ( unsigned portCHAR ) 1 )
\r
117 #define portBIT_CLEAR ( ( unsigned portCHAR ) 0 )
\r
120 * The serial port ISR's are defined in serial.c, but are called from portable
\r
121 * as they use the same vector as the tick ISR.
\r
123 void vSerialTxISR( void );
\r
124 void vSerialRxISR( void );
\r
127 * Perform hardware setup to enable ticks.
\r
129 static void prvSetupTimerInterrupt( void );
\r
132 * ISR to maintain the tick, and perform tick context switches if the
\r
133 * preemptive scheduler is being used.
\r
135 static void prvTickISR( void );
\r
138 * ISR placed on the low priority vector. This calls the appropriate ISR for
\r
139 * the actual interrupt.
\r
141 static void prvLowInterrupt( void );
\r
144 * Macro that pushes all the registers that make up the context of a task onto
\r
145 * the stack, then saves the new top of stack into the TCB.
\r
147 * If this is called from an ISR then the interrupt enable bits must have been
\r
148 * set for the ISR to ever get called. Therefore we want to save the INTCON
\r
149 * register with the enable bits forced to be set - and ucForcedInterruptFlags
\r
150 * must contain these bit settings. This means the interrupts will again be
\r
151 * enabled when the interrupted task is switched back in.
\r
153 * If this is called from a manual context switch (i.e. from a call to yield),
\r
154 * then we want to save the INTCON so it is restored with its current state,
\r
155 * and ucForcedInterruptFlags must be 0. This allows a yield from within
\r
156 * a critical section.
\r
158 * The compiler uses some locations at the bottom of the memory for temporary
\r
159 * storage during math and other computations. This is especially true if
\r
160 * 32bit data types are utilised (as they are by the scheduler). The .tmpdata
\r
161 * and MATH_DATA sections have to be stored in there entirety as part of a task
\r
162 * context. This macro stores from data address 0x00 to
\r
163 * portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
\r
164 * applications but you should check the map file for your project to ensure
\r
165 * this is sufficient for your needs. It is not clear whether this size is
\r
166 * fixed for all compilations or has the potential to be program specific.
\r
168 #define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
\r
171 /* Save the status and WREG registers first, as these will get modified \
\r
172 by the operations below. */ \
\r
173 MOVFF WREG, PREINC1 \
\r
174 MOVFF STATUS, PREINC1 \
\r
175 /* Save the INTCON register with the appropriate bits forced if \
\r
176 necessary - as described above. */ \
\r
177 MOVFF INTCON, WREG \
\r
178 IORLW ucForcedInterruptFlags \
\r
179 MOVFF WREG, PREINC1 \
\r
182 portDISABLE_INTERRUPTS(); \
\r
185 /* Store the necessary registers to the stack. */ \
\r
186 MOVFF BSR, PREINC1 \
\r
187 MOVFF FSR2L, PREINC1 \
\r
188 MOVFF FSR2H, PREINC1 \
\r
189 MOVFF FSR0L, PREINC1 \
\r
190 MOVFF FSR0H, PREINC1 \
\r
191 MOVFF TABLAT, PREINC1 \
\r
192 MOVFF TBLPTRU, PREINC1 \
\r
193 MOVFF TBLPTRH, PREINC1 \
\r
194 MOVFF TBLPTRL, PREINC1 \
\r
195 MOVFF PRODH, PREINC1 \
\r
196 MOVFF PRODL, PREINC1 \
\r
197 MOVFF PCLATU, PREINC1 \
\r
198 MOVFF PCLATH, PREINC1 \
\r
199 /* Store the .tempdata and MATH_DATA areas as described above. */ \
\r
202 MOVFF POSTINC0, PREINC1 \
\r
203 MOVFF POSTINC0, PREINC1 \
\r
204 MOVFF POSTINC0, PREINC1 \
\r
205 MOVFF POSTINC0, PREINC1 \
\r
206 MOVFF POSTINC0, PREINC1 \
\r
207 MOVFF POSTINC0, PREINC1 \
\r
208 MOVFF POSTINC0, PREINC1 \
\r
209 MOVFF POSTINC0, PREINC1 \
\r
210 MOVFF POSTINC0, PREINC1 \
\r
211 MOVFF POSTINC0, PREINC1 \
\r
212 MOVFF POSTINC0, PREINC1 \
\r
213 MOVFF POSTINC0, PREINC1 \
\r
214 MOVFF POSTINC0, PREINC1 \
\r
215 MOVFF POSTINC0, PREINC1 \
\r
216 MOVFF POSTINC0, PREINC1 \
\r
217 MOVFF POSTINC0, PREINC1 \
\r
218 MOVFF POSTINC0, PREINC1 \
\r
219 MOVFF POSTINC0, PREINC1 \
\r
220 MOVFF POSTINC0, PREINC1 \
\r
221 MOVFF INDF0, PREINC1 \
\r
222 MOVFF FSR0L, PREINC1 \
\r
223 MOVFF FSR0H, PREINC1 \
\r
224 /* Store the hardware stack pointer in a temp register before we \
\r
226 MOVFF STKPTR, FSR0L \
\r
229 /* Store each address from the hardware stack. */ \
\r
230 while( STKPTR > ( unsigned portCHAR ) 0 ) \
\r
233 MOVFF TOSL, PREINC1 \
\r
234 MOVFF TOSH, PREINC1 \
\r
235 MOVFF TOSU, PREINC1 \
\r
241 /* Store the number of addresses on the hardware stack (from the \
\r
242 temporary register). */ \
\r
243 MOVFF FSR0L, PREINC1 \
\r
244 MOVF PREINC1, 1, 0 \
\r
247 /* Save the new top of the software stack in the TCB. */ \
\r
249 MOVFF pxCurrentTCB, FSR0L \
\r
250 MOVFF pxCurrentTCB + 1, FSR0H \
\r
251 MOVFF FSR1L, POSTINC0 \
\r
252 MOVFF FSR1H, POSTINC0 \
\r
255 /*-----------------------------------------------------------*/
\r
258 * This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
\r
261 #define portRESTORE_CONTEXT() \
\r
264 /* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
\r
265 MOVFF pxCurrentTCB, FSR0L \
\r
266 MOVFF pxCurrentTCB + 1, FSR0H \
\r
268 /* De-reference FSR0 to set the address it holds into FSR1. \
\r
269 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
\r
270 MOVFF POSTINC0, FSR1L \
\r
271 MOVFF POSTINC0, FSR1H \
\r
273 /* How many return addresses are there on the hardware stack? Discard \
\r
274 the first byte as we are pointing to the next free space. */ \
\r
275 MOVFF POSTDEC1, FSR0L \
\r
276 MOVFF POSTDEC1, FSR0L \
\r
279 /* Fill the hardware stack from our software stack. */ \
\r
282 while( STKPTR < FSR0L ) \
\r
286 MOVF POSTDEC1, 0, 0 \
\r
288 MOVF POSTDEC1, 0, 0 \
\r
290 MOVF POSTDEC1, 0, 0 \
\r
296 /* Restore the .tmpdata and MATH_DATA memory. */ \
\r
297 MOVFF POSTDEC1, FSR0H \
\r
298 MOVFF POSTDEC1, FSR0L \
\r
299 MOVFF POSTDEC1, POSTDEC0 \
\r
300 MOVFF POSTDEC1, POSTDEC0 \
\r
301 MOVFF POSTDEC1, POSTDEC0 \
\r
302 MOVFF POSTDEC1, POSTDEC0 \
\r
303 MOVFF POSTDEC1, POSTDEC0 \
\r
304 MOVFF POSTDEC1, POSTDEC0 \
\r
305 MOVFF POSTDEC1, POSTDEC0 \
\r
306 MOVFF POSTDEC1, POSTDEC0 \
\r
307 MOVFF POSTDEC1, POSTDEC0 \
\r
308 MOVFF POSTDEC1, POSTDEC0 \
\r
309 MOVFF POSTDEC1, POSTDEC0 \
\r
310 MOVFF POSTDEC1, POSTDEC0 \
\r
311 MOVFF POSTDEC1, POSTDEC0 \
\r
312 MOVFF POSTDEC1, POSTDEC0 \
\r
313 MOVFF POSTDEC1, POSTDEC0 \
\r
314 MOVFF POSTDEC1, POSTDEC0 \
\r
315 MOVFF POSTDEC1, POSTDEC0 \
\r
316 MOVFF POSTDEC1, POSTDEC0 \
\r
317 MOVFF POSTDEC1, POSTDEC0 \
\r
318 MOVFF POSTDEC1, INDF0 \
\r
319 /* Restore the other registers forming the tasks context. */ \
\r
320 MOVFF POSTDEC1, PCLATH \
\r
321 MOVFF POSTDEC1, PCLATU \
\r
322 MOVFF POSTDEC1, PRODL \
\r
323 MOVFF POSTDEC1, PRODH \
\r
324 MOVFF POSTDEC1, TBLPTRL \
\r
325 MOVFF POSTDEC1, TBLPTRH \
\r
326 MOVFF POSTDEC1, TBLPTRU \
\r
327 MOVFF POSTDEC1, TABLAT \
\r
328 MOVFF POSTDEC1, FSR0H \
\r
329 MOVFF POSTDEC1, FSR0L \
\r
330 MOVFF POSTDEC1, FSR2H \
\r
331 MOVFF POSTDEC1, FSR2L \
\r
332 MOVFF POSTDEC1, BSR \
\r
333 /* The next byte is the INTCON register. Read this into WREG as some \
\r
334 manipulation is required. */ \
\r
335 MOVFF POSTDEC1, WREG \
\r
338 /* From the INTCON register, only the interrupt enable bits form part \
\r
339 of the tasks context. It is perfectly legitimate for another task to \
\r
340 have modified any other bits. We therefore only restore the top two bits. \
\r
342 if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
\r
345 MOVFF POSTDEC1, STATUS \
\r
346 MOVFF POSTDEC1, WREG \
\r
347 /* Return enabling interrupts. */ \
\r
354 MOVFF POSTDEC1, STATUS \
\r
355 MOVFF POSTDEC1, WREG \
\r
356 /* Return without effecting interrupts. The context may have \
\r
357 been saved from a critical region. */ \
\r
362 /*-----------------------------------------------------------*/
\r
365 * See header file for description.
\r
367 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
\r
369 unsigned portLONG ulAddress;
\r
370 unsigned portCHAR ucBlock;
\r
372 /* Place a few bytes of known values on the bottom of the stack.
\r
373 This is just useful for debugging. */
\r
375 *pxTopOfStack = 0x11;
\r
377 *pxTopOfStack = 0x22;
\r
379 *pxTopOfStack = 0x33;
\r
383 /* Simulate how the stack would look after a call to vPortYield() generated
\r
386 First store the function parameters. This is where the task will expect to
\r
387 find them when it starts running. */
\r
388 ulAddress = ( unsigned portLONG ) pvParameters;
\r
389 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );
\r
393 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );
\r
396 /* Next we just leave a space. When a context is saved the stack pointer
\r
397 is incremented before it is used so as not to corrupt whatever the stack
\r
398 pointer is actually pointing to. This is especially necessary during
\r
399 function epilogue code generated by the compiler. */
\r
400 *pxTopOfStack = 0x44;
\r
403 /* Next are all the registers that form part of the task context. */
\r
405 *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* WREG. */
\r
408 *pxTopOfStack = ( portSTACK_TYPE ) 0xcc; /* Status. */
\r
411 /* INTCON is saved with interrupts enabled. */
\r
412 *pxTopOfStack = ( portSTACK_TYPE ) portINITAL_INTERRUPT_STATE; /* INTCON */
\r
415 *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* BSR. */
\r
418 *pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* FSR2L. */
\r
421 *pxTopOfStack = ( portSTACK_TYPE ) 0x33; /* FSR2H. */
\r
424 *pxTopOfStack = ( portSTACK_TYPE ) 0x44; /* FSR0L. */
\r
427 *pxTopOfStack = ( portSTACK_TYPE ) 0x55; /* FSR0H. */
\r
430 *pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* TABLAT. */
\r
433 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */
\r
436 *pxTopOfStack = ( portSTACK_TYPE ) 0x88; /* TBLPTRUH. */
\r
439 *pxTopOfStack = ( portSTACK_TYPE ) 0x99; /* TBLPTRUL. */
\r
442 *pxTopOfStack = ( portSTACK_TYPE ) 0xaa; /* PRODH. */
\r
445 *pxTopOfStack = ( portSTACK_TYPE ) 0xbb; /* PRODL. */
\r
448 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATU. */
\r
451 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATH. */
\r
454 /* Next the .tmpdata and MATH_DATA sections. */
\r
455 for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
\r
457 *pxTopOfStack = ( portSTACK_TYPE ) ucBlock;
\r
461 /* Store the top of the global data section. */
\r
462 *pxTopOfStack = ( portSTACK_TYPE ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
\r
465 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* High. */
\r
468 /* The only function return address so far is the address of the
\r
470 ulAddress = ( unsigned portLONG ) pxCode;
\r
473 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );
\r
478 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );
\r
482 /* TOS even higher. */
\r
483 *pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned portLONG ) 0x00ff );
\r
486 /* Store the number of return addresses on the hardware stack - so far only
\r
487 the address of the task entry point. */
\r
488 *pxTopOfStack = ( portSTACK_TYPE ) 1;
\r
491 return pxTopOfStack;
\r
493 /*-----------------------------------------------------------*/
\r
495 portBASE_TYPE xPortStartScheduler( void )
\r
497 /* Setup a timer for the tick ISR is using the preemptive scheduler. */
\r
498 prvSetupTimerInterrupt();
\r
500 /* Restore the context of the first task to run. */
\r
501 portRESTORE_CONTEXT();
\r
503 /* Should not get here. Use the function name to stop compiler warnings. */
\r
504 ( void ) prvLowInterrupt;
\r
505 ( void ) prvTickISR;
\r
509 /*-----------------------------------------------------------*/
\r
511 void vPortEndScheduler( void )
\r
513 /* It is unlikely that the scheduler for the PIC port will get stopped
\r
514 once running. If required disable the tick interrupt here, then return
\r
515 to xPortStartScheduler(). */
\r
517 /*-----------------------------------------------------------*/
\r
520 * Manual context switch. This is similar to the tick context switch,
\r
521 * but does not increment the tick count. It must be identical to the
\r
522 * tick context switch in how it stores the stack of a task.
\r
524 void vPortYield( void )
\r
526 /* This can get called with interrupts either enabled or disabled. We
\r
527 will save the INTCON register with the interrupt enable bits unmodified. */
\r
528 portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
\r
530 /* Switch to the highest priority task that is ready to run. */
\r
531 vTaskSwitchContext();
\r
533 /* Start executing the task we have just switched to. */
\r
534 portRESTORE_CONTEXT();
\r
536 /*-----------------------------------------------------------*/
\r
539 * Vector for ISR. Nothing here must alter any registers!
\r
541 #pragma code high_vector=0x08
\r
542 static void prvLowInterrupt( void )
\r
544 /* Was the interrupt the tick? */
\r
545 if( PIR1bits.CCP1IF )
\r
552 /* Was the interrupt a byte being received? */
\r
553 if( PIR1bits.RCIF )
\r
560 /* Was the interrupt the Tx register becoming empty? */
\r
561 if( PIR1bits.TXIF )
\r
563 if( PIE1bits.TXIE )
\r
573 /*-----------------------------------------------------------*/
\r
576 * ISR for the tick.
\r
577 * This increments the tick count and, if using the preemptive scheduler,
\r
578 * performs a context switch. This must be identical to the manual
\r
579 * context switch in how it stores the context of a task.
\r
581 static void prvTickISR( void )
\r
583 /* Interrupts must have been enabled for the ISR to fire, so we have to
\r
584 save the context with interrupts enabled. */
\r
585 portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
\r
586 PIR1bits.CCP1IF = 0;
\r
588 /* Maintain the tick count. */
\r
589 vTaskIncrementTick();
\r
591 #if configUSE_PREEMPTION == 1
\r
593 /* Switch to the highest priority task that is ready to run. */
\r
594 vTaskSwitchContext();
\r
598 portRESTORE_CONTEXT();
\r
600 /*-----------------------------------------------------------*/
\r
603 * Setup a timer for a regular tick.
\r
605 static void prvSetupTimerInterrupt( void )
\r
607 const unsigned portLONG ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
\r
608 unsigned portLONG ulCompareValue;
\r
609 unsigned portCHAR ucByte;
\r
611 /* Interrupts are disabled when this function is called.
\r
613 Setup CCP1 to provide the tick interrupt using a compare match on timer
\r
616 Clear the time count then setup timer. */
\r
617 TMR1H = ( unsigned portCHAR ) 0x00;
\r
618 TMR1L = ( unsigned portCHAR ) 0x00;
\r
620 /* Set the compare match value. */
\r
621 ulCompareValue = ulConstCompareValue;
\r
622 CCPR1L = ( unsigned portCHAR ) ( ulCompareValue & ( unsigned portLONG ) 0xff );
\r
623 ulCompareValue >>= ( unsigned portLONG ) 8;
\r
624 CCPR1H = ( unsigned portCHAR ) ( ulCompareValue & ( unsigned portLONG ) 0xff );
\r
626 CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
\r
627 CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
\r
628 CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
\r
629 CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
\r
630 PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
\r
632 /* We are only going to use the global interrupt bit, so set the peripheral
\r
634 INTCONbits.GIEL = portBIT_SET;
\r
636 /* Provided library function for setting up the timer that will produce the
\r
638 OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
\r
projects / freertos / blob