2 FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd.
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4 ***************************************************************************
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8 * + New to FreeRTOS, *
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10 * + Looking for basic training, *
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11 * + Wanting to improve your FreeRTOS skills and productivity *
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13 * then take a look at the FreeRTOS eBook *
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15 * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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16 * http://www.FreeRTOS.org/Documentation *
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18 * A pdf reference manual is also available. Both are usually delivered *
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19 * to your inbox within 20 minutes to two hours when purchased between 8am *
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20 * and 8pm GMT (although please allow up to 24 hours in case of *
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21 * exceptional circumstances). Thank you for your support! *
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23 ***************************************************************************
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25 This file is part of the FreeRTOS distribution.
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27 FreeRTOS is free software; you can redistribute it and/or modify it under
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28 the terms of the GNU General Public License (version 2) as published by the
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29 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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30 ***NOTE*** The exception to the GPL is included to allow you to distribute
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31 a combined work that includes FreeRTOS without being obliged to provide the
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32 source code for proprietary components outside of the FreeRTOS kernel.
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33 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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34 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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35 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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36 more details. You should have received a copy of the GNU General Public
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37 License and the FreeRTOS license exception along with FreeRTOS; if not it
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38 can be viewed here: http://www.freertos.org/a00114.html and also obtained
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39 by writing to Richard Barry, contact details for whom are available on the
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44 http://www.FreeRTOS.org - Documentation, latest information, license and
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47 http://www.SafeRTOS.com - A version that is certified for use in safety
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50 http://www.OpenRTOS.com - Commercial support, development, porting,
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51 licensing and training services.
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54 #include <p32xxxx.h>
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55 #include <sys/asm.h>
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56 #include "ISR_Support.h"
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62 .extern pxCurrentTCB
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63 .extern vTaskSwitchContext
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64 .extern vPortIncrementTick
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65 .extern xISRStackTop
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67 .global vPortStartFirstTask
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68 .global vPortYieldISR
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69 .global vT1InterruptHandler
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72 /******************************************************************/
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74 .section .FreeRTOS, "ax", @progbits
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77 .ent vT1InterruptHandler
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79 vT1InterruptHandler:
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83 jal vPortIncrementTick
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88 .end vT1InterruptHandler
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90 /******************************************************************/
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92 .section .FreeRTOS, "ax", @progbits
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95 .ent xPortStartScheduler
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97 vPortStartFirstTask:
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99 /* Simply restore the context of the highest priority task that has been
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101 portRESTORE_CONTEXT
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103 .end xPortStartScheduler
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107 /*******************************************************************/
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109 .section .FreeRTOS, "ax", @progbits
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116 /* Make room for the context. First save the current status so we can
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117 manipulate it, and the cause and EPC registers so we capture their
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118 original values in case of interrupt nesting. */
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119 mfc0 k0, _CP0_CAUSE
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120 addiu sp, sp, -portCONTEXT_SIZE
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121 mfc0 k1, _CP0_STATUS
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123 /* Also save s6 and s5 so we can use them during this interrupt. Any
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124 nesting interrupts should maintain the values of these registers
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128 sw k1, portSTATUS_STACK_LOCATION(sp)
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130 /* Enable interrupts above the current priority. */
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135 /* s5 is used as the frame pointer. */
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138 /* Swap to the system stack. This is not conditional on the nesting
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139 count as this interrupt is always the lowest priority and therefore
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140 the nesting is always 0. */
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141 la sp, xISRStackTop
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144 /* Set the nesting count. */
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145 la k0, uxInterruptNesting
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149 /* s6 holds the EPC value, this is saved with the rest of the context
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150 after interrupts are enabled. */
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153 /* Re-enable interrupts. */
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154 mtc0 k1, _CP0_STATUS
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156 /* Save the context into the space just created. s6 is saved again
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157 here as it now contains the EPC value. */
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177 sw s6, portEPC_STACK_LOCATION(s5)
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178 /* s5 and s6 has already been saved. */
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186 /* s7 is used as a scratch register as this should always be saved across
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187 nesting interrupts. */
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193 /* Save the stack pointer to the task. */
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194 la s7, pxCurrentTCB
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198 /* Set the interrupt mask to the max priority that can use the API. */
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200 mfc0 s7, _CP0_STATUS
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202 ori s6, s7, configMAX_SYSCALL_INTERRUPT_PRIORITY << 10
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204 /* This mtc0 re-enables interrupts, but only above
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205 configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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206 mtc0 s6, _CP0_STATUS
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208 /* Clear the software interrupt in the core. */
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209 mfc0 s6, _CP0_CAUSE
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212 mtc0 s6, _CP0_CAUSE
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214 /* Clear the interrupt in the interrupt controller. */
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219 jal vTaskSwitchContext
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222 /* Clear the interrupt mask again. The saved status value is still in s7. */
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223 mtc0 s7, _CP0_STATUS
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225 /* Restore the stack pointer from the TCB. */
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226 la s0, pxCurrentTCB
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230 /* Restore the rest of the context. */
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241 /* s5 is loaded later. */
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263 /* Protect access to the k registers, and others. */
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266 /* Set nesting back to zero. As the lowest priority interrupt this
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267 interrupt cannot have nested. */
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268 la k0, uxInterruptNesting
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271 /* Switch back to use the real stack pointer. */
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274 /* Restore the real s5 value. */
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277 /* Pop the status and epc values. */
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278 lw k1, portSTATUS_STACK_LOCATION(sp)
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279 lw k0, portEPC_STACK_LOCATION(sp)
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281 /* Remove stack frame. */
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282 addiu sp, sp, portCONTEXT_SIZE
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284 mtc0 k1, _CP0_STATUS
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