git.sur5r.net Git - u-boot/blob - arch/arc/dts/hsdk.dts

   1 /*
   2  * Copyright (C) 2017 Synopsys, Inc. All rights reserved.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 /dts-v1/;
   7
   8 #include "skeleton.dtsi"
   9 #include "dt-bindings/clock/snps,hsdk-cgu.h"
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         aliases {
  16                 console = &uart0;
  17         };
  18
  19         cpu_card {
  20                 core_clk: core_clk {
  21                         #clock-cells = <0>;
  22                         compatible = "fixed-clock";
  23                         clock-frequency = <1000000000>;
  24                         u-boot,dm-pre-reloc;
  25                 };
  26         };
  27
  28         clk-fmeas {
  29                 clocks = <&cgu_clk CLK_ARC_PLL>, <&cgu_clk CLK_SYS_PLL>,
  30                          <&cgu_clk CLK_TUN_PLL>, <&cgu_clk CLK_DDR_PLL>,
  31                          <&cgu_clk CLK_ARC>, <&cgu_clk CLK_HDMI_PLL>,
  32                          <&cgu_clk CLK_TUN_TUN>, <&cgu_clk CLK_HDMI>,
  33                          <&cgu_clk CLK_SYS_APB>, <&cgu_clk CLK_SYS_AXI>,
  34                          <&cgu_clk CLK_SYS_ETH>, <&cgu_clk CLK_SYS_USB>,
  35                          <&cgu_clk CLK_SYS_SDIO>, <&cgu_clk CLK_SYS_HDMI>,
  36                          <&cgu_clk CLK_SYS_GFX_CORE>, <&cgu_clk CLK_SYS_GFX_DMA>,
  37                          <&cgu_clk CLK_SYS_GFX_CFG>, <&cgu_clk CLK_SYS_DMAC_CORE>,
  38                          <&cgu_clk CLK_SYS_DMAC_CFG>, <&cgu_clk CLK_SYS_SDIO_REF>,
  39                          <&cgu_clk CLK_SYS_SPI_REF>, <&cgu_clk CLK_SYS_I2C_REF>,
  40                          <&cgu_clk CLK_SYS_UART_REF>, <&cgu_clk CLK_SYS_EBI_REF>,
  41                          <&cgu_clk CLK_TUN_ROM>, <&cgu_clk CLK_TUN_PWM>;
  42                 clock-names = "cpu-pll", "sys-pll",
  43                               "tun-pll", "ddr-clk",
  44                               "cpu-clk", "hdmi-pll",
  45                               "tun-clk", "hdmi-clk",
  46                               "apb-clk", "axi-clk",
  47                               "eth-clk", "usb-clk",
  48                               "sdio-clk", "hdmi-sys-clk",
  49                               "gfx-core-clk", "gfx-dma-clk",
  50                               "gfx-cfg-clk", "dmac-core-clk",
  51                               "dmac-cfg-clk", "sdio-ref-clk",
  52                               "spi-clk", "i2c-clk",
  53                               "uart-clk", "ebi-clk",
  54                               "rom-clk", "pwm-clk";
  55         };
  56
  57         cgu_clk: cgu-clk@f0000000 {
  58                 compatible = "snps,hsdk-cgu-clock";
  59                 reg = <0xf0000000 0x10>, <0xf00014B8 0x4>;
  60                 #clock-cells = <1>;
  61         };
  62
  63         uart0: serial0@f0005000 {
  64                 compatible = "snps,dw-apb-uart";
  65                 reg = <0xf0005000 0x1000>;
  66                 reg-shift = <2>;
  67                 reg-io-width = <4>;
  68         };
  69
  70         ethernet@f0008000 {
  71                 #interrupt-cells = <1>;
  72                 compatible = "altr,socfpga-stmmac";
  73                 reg = <0xf0008000 0x2000>;
  74                 phy-mode = "gmii";
  75         };
  76
  77         ehci@0xf0040000 {
  78                 compatible = "generic-ehci";
  79                 reg = <0xf0040000 0x100>;
  80         };
  81
  82         ohci@0xf0060000 {
  83                 compatible = "generic-ohci";
  84                 reg = <0xf0060000 0x100>;
  85         };
  86 };