2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/compiler.h>
10 #include <linux/kernel.h>
11 #include <linux/log2.h>
12 #include <asm/arcregs.h>
13 #include <asm/cache.h>
15 /* Bit values in IC_CTRL */
16 #define IC_CTRL_CACHE_DISABLE BIT(0)
18 /* Bit values in DC_CTRL */
19 #define DC_CTRL_CACHE_DISABLE BIT(0)
20 #define DC_CTRL_INV_MODE_FLUSH BIT(6)
21 #define DC_CTRL_FLUSH_STATUS BIT(8)
22 #define CACHE_VER_NUM_MASK 0xF
28 /* Bit val in SLC_CONTROL */
29 #define SLC_CTRL_DIS 0x001
30 #define SLC_CTRL_IM 0x040
31 #define SLC_CTRL_BUSY 0x100
32 #define SLC_CTRL_RGN_OP_INV 0x200
35 * By default that variable will fall into .bss section.
36 * But .bss section is not relocated and so it will be initilized before
37 * relocation but will be used after being zeroed.
39 int l1_line_sz __section(".data");
40 bool dcache_exists __section(".data") = false;
41 bool icache_exists __section(".data") = false;
43 #define CACHE_LINE_MASK (~(l1_line_sz - 1))
45 #ifdef CONFIG_ISA_ARCV2
46 int slc_line_sz __section(".data");
47 bool slc_exists __section(".data") = false;
48 bool ioc_exists __section(".data") = false;
49 bool pae_exists __section(".data") = false;
51 /* To force enable IOC set ioc_enable to 'true' */
52 bool ioc_enable __section(".data") = false;
54 void read_decode_mmu_bcr(void)
56 /* TODO: should we compare mmu version from BCR and from CONFIG? */
57 #if (CONFIG_ARC_MMU_VER >= 4)
60 tmp = read_aux_reg(ARC_AUX_MMU_BCR);
63 #ifdef CONFIG_CPU_BIG_ENDIAN
64 unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
65 n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
67 /* DTLB ITLB JES JE JA */
68 unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
69 pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
70 #endif /* CONFIG_CPU_BIG_ENDIAN */
73 mmu4 = (struct bcr_mmu_4 *)&tmp;
75 pae_exists = !!mmu4->pae;
76 #endif /* (CONFIG_ARC_MMU_VER >= 4) */
79 static void __slc_entire_op(const int op)
83 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
85 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
86 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
90 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
92 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
93 write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1);
95 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1);
97 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
98 read_aux_reg(ARC_AUX_SLC_CTRL);
100 /* Important to wait for flush to complete */
101 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
104 static void slc_upper_region_init(void)
107 * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0
108 * as we don't use PAE40.
110 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0);
111 write_aux_reg(ARC_AUX_SLC_RGN_START1, 0);
114 static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
120 * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
121 * - b'000 (default) is Flush,
122 * - b'001 is Invalidate if CTRL.IM == 0
123 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1
125 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
127 /* Don't rely on default value of IM bit */
128 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
129 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
134 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
136 ctrl &= ~SLC_CTRL_RGN_OP_INV;
138 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
141 * Lower bits are ignored, no need to clip
142 * END needs to be setup before START (latter triggers the operation)
143 * END can't be same as START, so add (l2_line_sz - 1) to sz
145 end = paddr + sz + slc_line_sz - 1;
148 * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1)
149 * are always == 0 as we don't use PAE40, so we only setup lower ones
150 * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START)
152 write_aux_reg(ARC_AUX_SLC_RGN_END, end);
153 write_aux_reg(ARC_AUX_SLC_RGN_START, paddr);
155 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
156 read_aux_reg(ARC_AUX_SLC_CTRL);
158 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
160 #endif /* CONFIG_ISA_ARCV2 */
162 #ifdef CONFIG_ISA_ARCV2
163 static void read_decode_cache_bcr_arcv2(void)
167 #ifdef CONFIG_CPU_BIG_ENDIAN
168 unsigned int pad:24, way:2, lsz:2, sz:4;
170 unsigned int sz:4, lsz:2, way:2, pad:24;
178 #ifdef CONFIG_CPU_BIG_ENDIAN
179 unsigned int pad:24, ver:8;
181 unsigned int ver:8, pad:24;
187 sbcr.word = read_aux_reg(ARC_BCR_SLC);
188 if (sbcr.fields.ver) {
189 slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
191 slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
195 struct bcr_clust_cfg {
196 #ifdef CONFIG_CPU_BIG_ENDIAN
197 unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
199 unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
205 cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
206 if (cbcr.fields.c && ioc_enable)
211 void read_decode_cache_bcr(void)
213 int dc_line_sz = 0, ic_line_sz = 0;
217 #ifdef CONFIG_CPU_BIG_ENDIAN
218 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
220 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
226 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
227 if (ibcr.fields.ver) {
228 icache_exists = true;
229 l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
231 panic("Instruction exists but line length is 0\n");
234 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
235 if (dbcr.fields.ver) {
236 dcache_exists = true;
237 l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
239 panic("Data cache exists but line length is 0\n");
242 if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz))
243 panic("Instruction and data cache line lengths differ\n");
246 void cache_init(void)
248 read_decode_cache_bcr();
250 #ifdef CONFIG_ISA_ARCV2
251 read_decode_cache_bcr_arcv2();
254 /* IOC Aperture start is equal to DDR start */
255 unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
256 /* IOC Aperture size is equal to DDR size */
257 long ap_size = CONFIG_SYS_SDRAM_SIZE;
260 invalidate_dcache_all();
262 if (!is_power_of_2(ap_size) || ap_size < 4096)
263 panic("IOC Aperture size must be power of 2 and bigger 4Kib");
266 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
267 * so setting 0x11 implies 512M, 0x12 implies 1G...
269 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
270 order_base_2(ap_size / 1024) - 2);
272 /* IOC Aperture start must be aligned to the size of the aperture */
273 if (ap_base % ap_size != 0)
274 panic("IOC Aperture start must be aligned to the size of the aperture");
276 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
277 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
278 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
281 read_decode_mmu_bcr();
284 * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
285 * only if PAE exists in current HW. So we had to check pae_exist
288 if (slc_exists && pae_exists)
289 slc_upper_region_init();
290 #endif /* CONFIG_ISA_ARCV2 */
293 int icache_status(void)
298 if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
304 void icache_enable(void)
307 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
308 ~IC_CTRL_CACHE_DISABLE);
311 void icache_disable(void)
314 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
315 IC_CTRL_CACHE_DISABLE);
318 /* IC supports only invalidation */
319 static inline void __ic_entire_invalidate(void)
321 if (!icache_status())
324 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
325 write_aux_reg(ARC_AUX_IC_IVIC, 1);
327 * As per ARC HS databook (see chapter 5.3.3.2)
328 * it is required to add 3 NOPs after each write to IC_IVIC.
333 read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
336 void invalidate_icache_all(void)
338 __ic_entire_invalidate();
340 #ifdef CONFIG_ISA_ARCV2
342 __slc_entire_op(OP_INV);
346 int dcache_status(void)
351 if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
357 void dcache_enable(void)
362 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
363 ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
366 void dcache_disable(void)
371 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
372 DC_CTRL_CACHE_DISABLE);
375 #ifndef CONFIG_SYS_DCACHE_OFF
377 * Common Helper for Line Operations on {I,D}-Cache
379 static inline void __cache_line_loop(unsigned long paddr, unsigned long sz,
382 unsigned int aux_cmd;
383 #if (CONFIG_ARC_MMU_VER == 3)
384 unsigned int aux_tag;
388 if (cacheop == OP_INV_IC) {
389 aux_cmd = ARC_AUX_IC_IVIL;
390 #if (CONFIG_ARC_MMU_VER == 3)
391 aux_tag = ARC_AUX_IC_PTAG;
394 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
395 aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
396 #if (CONFIG_ARC_MMU_VER == 3)
397 aux_tag = ARC_AUX_DC_PTAG;
401 sz += paddr & ~CACHE_LINE_MASK;
402 paddr &= CACHE_LINE_MASK;
404 num_lines = DIV_ROUND_UP(sz, l1_line_sz);
406 while (num_lines-- > 0) {
407 #if (CONFIG_ARC_MMU_VER == 3)
408 write_aux_reg(aux_tag, paddr);
410 write_aux_reg(aux_cmd, paddr);
415 static unsigned int __before_dc_op(const int op)
421 * IM is set by default and implies Flush-n-inv
422 * Clear it here for vanilla inv
424 reg = read_aux_reg(ARC_AUX_DC_CTRL);
425 write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
431 static void __after_dc_op(const int op, unsigned int reg)
433 if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
434 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
436 /* Switch back to default Invalidate mode */
438 write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
441 static inline void __dc_entire_op(const int cacheop)
444 unsigned int ctrl_reg = __before_dc_op(cacheop);
446 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
447 aux = ARC_AUX_DC_IVDC;
449 aux = ARC_AUX_DC_FLSH;
451 write_aux_reg(aux, 0x1);
453 __after_dc_op(cacheop, ctrl_reg);
456 static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
459 unsigned int ctrl_reg = __before_dc_op(cacheop);
461 __cache_line_loop(paddr, sz, cacheop);
462 __after_dc_op(cacheop, ctrl_reg);
465 #define __dc_entire_op(cacheop)
466 #define __dc_line_op(paddr, sz, cacheop)
467 #endif /* !CONFIG_SYS_DCACHE_OFF */
469 void invalidate_dcache_range(unsigned long start, unsigned long end)
474 #ifdef CONFIG_ISA_ARCV2
477 __dc_line_op(start, end - start, OP_INV);
479 #ifdef CONFIG_ISA_ARCV2
480 if (slc_exists && !ioc_exists)
481 __slc_rgn_op(start, end - start, OP_INV);
485 void flush_dcache_range(unsigned long start, unsigned long end)
490 #ifdef CONFIG_ISA_ARCV2
493 __dc_line_op(start, end - start, OP_FLUSH);
495 #ifdef CONFIG_ISA_ARCV2
496 if (slc_exists && !ioc_exists)
497 __slc_rgn_op(start, end - start, OP_FLUSH);
501 void flush_cache(unsigned long start, unsigned long size)
503 flush_dcache_range(start, start + size);
506 void invalidate_dcache_all(void)
508 __dc_entire_op(OP_INV);
510 #ifdef CONFIG_ISA_ARCV2
512 __slc_entire_op(OP_INV);
516 void flush_dcache_all(void)
518 __dc_entire_op(OP_FLUSH);
520 #ifdef CONFIG_ISA_ARCV2
522 __slc_entire_op(OP_FLUSH);