2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/compiler.h>
10 #include <linux/kernel.h>
11 #include <linux/log2.h>
12 #include <asm/arcregs.h>
13 #include <asm/arc-bcr.h>
14 #include <asm/cache.h>
18 * Data cache (L1 D$ or SL$) entire invalidate operation or data cache disable
19 * operation may result in unexpected behavior and data loss even if we flush
20 * data cache right before invalidation. That may happens if we store any context
21 * on stack (like we store BLINK register on stack before function call).
22 * BLINK register is the register where return address is automatically saved
23 * when we do function call with instructions like 'bl'.
25 * There is the real example:
26 * We may hang in the next code as we store any BLINK register on stack in
27 * invalidate_dcache_all() function.
29 * void flush_dcache_all() {
30 * __dc_entire_op(OP_FLUSH);
34 * void invalidate_dcache_all() {
35 * __dc_entire_op(OP_INV);
41 * invalidate_dcache_all();
44 * Now let's see what really happens during that code execution:
47 * |->> call flush_dcache_all
48 * [return address is saved to BLINK register]
49 * [push BLINK] (save to stack) ![point 1]
50 * |->> call __dc_entire_op(OP_FLUSH)
51 * [return address is saved to BLINK register]
53 * return [jump to BLINK]
55 * [other flush_dcache_all code]
56 * [pop BLINK] (get from stack)
57 * return [jump to BLINK]
59 * |->> call invalidate_dcache_all
60 * [return address is saved to BLINK register]
61 * [push BLINK] (save to stack) ![point 2]
62 * |->> call __dc_entire_op(OP_FLUSH)
63 * [return address is saved to BLINK register]
64 * [invalidate L1 D$] ![point 3]
66 * // We lose return address from invalidate_dcache_all function:
67 * // we save it to stack and invalidate L1 D$ after that!
68 * return [jump to BLINK]
70 * [other invalidate_dcache_all code]
71 * [pop BLINK] (get from stack)
72 * // we don't have this data in L1 dcache as we invalidated it in [point 3]
73 * // so we get it from next memory level (for example DDR memory)
74 * // but in the memory we have value which we save in [point 1], which
75 * // is return address from flush_dcache_all function (instead of
76 * // address from current invalidate_dcache_all function which we
77 * // saved in [point 2] !)
78 * return [jump to BLINK]
80 * // As BLINK points to invalidate_dcache_all, we call it again and
83 * Fortunately we may fix that by using flush & invalidation of D$ with a single
84 * one instruction (instead of flush and invalidation instructions pair) and
85 * enabling force function inline with '__attribute__((always_inline))' gcc
86 * attribute to avoid any function call (and BLINK store) between cache flush
90 /* Bit values in IC_CTRL */
91 #define IC_CTRL_CACHE_DISABLE BIT(0)
93 /* Bit values in DC_CTRL */
94 #define DC_CTRL_CACHE_DISABLE BIT(0)
95 #define DC_CTRL_INV_MODE_FLUSH BIT(6)
96 #define DC_CTRL_FLUSH_STATUS BIT(8)
97 #define CACHE_VER_NUM_MASK 0xF
100 #define OP_FLUSH BIT(1)
101 #define OP_FLUSH_N_INV (OP_FLUSH | OP_INV)
103 /* Bit val in SLC_CONTROL */
104 #define SLC_CTRL_DIS 0x001
105 #define SLC_CTRL_IM 0x040
106 #define SLC_CTRL_BUSY 0x100
107 #define SLC_CTRL_RGN_OP_INV 0x200
110 * By default that variable will fall into .bss section.
111 * But .bss section is not relocated and so it will be initilized before
112 * relocation but will be used after being zeroed.
114 int l1_line_sz __section(".data");
115 bool dcache_exists __section(".data") = false;
116 bool icache_exists __section(".data") = false;
118 #define CACHE_LINE_MASK (~(l1_line_sz - 1))
120 #ifdef CONFIG_ISA_ARCV2
121 int slc_line_sz __section(".data");
122 bool slc_exists __section(".data") = false;
123 bool ioc_exists __section(".data") = false;
124 bool pae_exists __section(".data") = false;
126 /* To force enable IOC set ioc_enable to 'true' */
127 bool ioc_enable __section(".data") = false;
129 void read_decode_mmu_bcr(void)
131 /* TODO: should we compare mmu version from BCR and from CONFIG? */
132 #if (CONFIG_ARC_MMU_VER >= 4)
133 union bcr_mmu_4 mmu4;
135 mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR);
137 pae_exists = !!mmu4.fields.pae;
138 #endif /* (CONFIG_ARC_MMU_VER >= 4) */
141 static void __slc_entire_op(const int op)
145 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
147 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
148 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
152 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
154 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
155 write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1);
157 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1);
159 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
160 read_aux_reg(ARC_AUX_SLC_CTRL);
162 /* Important to wait for flush to complete */
163 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
166 static void slc_upper_region_init(void)
169 * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0
170 * as we don't use PAE40.
172 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0);
173 write_aux_reg(ARC_AUX_SLC_RGN_START1, 0);
176 static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
182 * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
183 * - b'000 (default) is Flush,
184 * - b'001 is Invalidate if CTRL.IM == 0
185 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1
187 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
189 /* Don't rely on default value of IM bit */
190 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
191 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
196 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
198 ctrl &= ~SLC_CTRL_RGN_OP_INV;
200 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
203 * Lower bits are ignored, no need to clip
204 * END needs to be setup before START (latter triggers the operation)
205 * END can't be same as START, so add (l2_line_sz - 1) to sz
207 end = paddr + sz + slc_line_sz - 1;
210 * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1)
211 * are always == 0 as we don't use PAE40, so we only setup lower ones
212 * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START)
214 write_aux_reg(ARC_AUX_SLC_RGN_END, end);
215 write_aux_reg(ARC_AUX_SLC_RGN_START, paddr);
217 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
218 read_aux_reg(ARC_AUX_SLC_CTRL);
220 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
223 static void arc_ioc_setup(void)
225 /* IOC Aperture start is equal to DDR start */
226 unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
227 /* IOC Aperture size is equal to DDR size */
228 long ap_size = CONFIG_SYS_SDRAM_SIZE;
230 flush_n_invalidate_dcache_all();
232 if (!is_power_of_2(ap_size) || ap_size < 4096)
233 panic("IOC Aperture size must be power of 2 and bigger 4Kib");
236 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
237 * so setting 0x11 implies 512M, 0x12 implies 1G...
239 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
240 order_base_2(ap_size / 1024) - 2);
242 /* IOC Aperture start must be aligned to the size of the aperture */
243 if (ap_base % ap_size != 0)
244 panic("IOC Aperture start must be aligned to the size of the aperture");
246 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
247 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
248 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
250 #endif /* CONFIG_ISA_ARCV2 */
252 #ifdef CONFIG_ISA_ARCV2
253 static void read_decode_cache_bcr_arcv2(void)
255 union bcr_slc_cfg slc_cfg;
256 union bcr_clust_cfg cbcr;
257 union bcr_generic sbcr;
259 sbcr.word = read_aux_reg(ARC_BCR_SLC);
260 if (sbcr.fields.ver) {
261 slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
263 slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
266 cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
267 if (cbcr.fields.c && ioc_enable)
272 void read_decode_cache_bcr(void)
274 int dc_line_sz = 0, ic_line_sz = 0;
275 union bcr_di_cache ibcr, dbcr;
277 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
278 if (ibcr.fields.ver) {
279 icache_exists = true;
280 l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
282 panic("Instruction exists but line length is 0\n");
285 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
286 if (dbcr.fields.ver) {
287 dcache_exists = true;
288 l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
290 panic("Data cache exists but line length is 0\n");
293 if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz))
294 panic("Instruction and data cache line lengths differ\n");
297 void cache_init(void)
299 read_decode_cache_bcr();
301 #ifdef CONFIG_ISA_ARCV2
302 read_decode_cache_bcr_arcv2();
307 read_decode_mmu_bcr();
310 * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
311 * only if PAE exists in current HW. So we had to check pae_exist
314 if (slc_exists && pae_exists)
315 slc_upper_region_init();
316 #endif /* CONFIG_ISA_ARCV2 */
319 int icache_status(void)
324 if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
330 void icache_enable(void)
333 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
334 ~IC_CTRL_CACHE_DISABLE);
337 void icache_disable(void)
340 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
341 IC_CTRL_CACHE_DISABLE);
344 /* IC supports only invalidation */
345 static inline void __ic_entire_invalidate(void)
347 if (!icache_status())
350 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
351 write_aux_reg(ARC_AUX_IC_IVIC, 1);
353 * As per ARC HS databook (see chapter 5.3.3.2)
354 * it is required to add 3 NOPs after each write to IC_IVIC.
359 read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
362 void invalidate_icache_all(void)
364 __ic_entire_invalidate();
366 #ifdef CONFIG_ISA_ARCV2
368 __slc_entire_op(OP_INV);
372 int dcache_status(void)
377 if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
383 void dcache_enable(void)
388 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
389 ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
392 void dcache_disable(void)
397 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
398 DC_CTRL_CACHE_DISABLE);
401 #ifndef CONFIG_SYS_DCACHE_OFF
402 /* Common Helper for Line Operations on D-cache */
403 static inline void __dcache_line_loop(unsigned long paddr, unsigned long sz,
406 unsigned int aux_cmd;
409 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
410 aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
412 sz += paddr & ~CACHE_LINE_MASK;
413 paddr &= CACHE_LINE_MASK;
415 num_lines = DIV_ROUND_UP(sz, l1_line_sz);
417 while (num_lines-- > 0) {
418 #if (CONFIG_ARC_MMU_VER == 3)
419 write_aux_reg(ARC_AUX_DC_PTAG, paddr);
421 write_aux_reg(aux_cmd, paddr);
426 static void __before_dc_op(const int op)
430 ctrl = read_aux_reg(ARC_AUX_DC_CTRL);
432 /* IM bit implies flush-n-inv, instead of vanilla inv */
434 ctrl &= ~DC_CTRL_INV_MODE_FLUSH;
436 ctrl |= DC_CTRL_INV_MODE_FLUSH;
438 write_aux_reg(ARC_AUX_DC_CTRL, ctrl);
441 static void __after_dc_op(const int op)
443 if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
444 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS);
447 static inline void __dc_entire_op(const int cacheop)
451 __before_dc_op(cacheop);
453 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
454 aux = ARC_AUX_DC_IVDC;
456 aux = ARC_AUX_DC_FLSH;
458 write_aux_reg(aux, 0x1);
460 __after_dc_op(cacheop);
463 static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
466 __before_dc_op(cacheop);
467 __dcache_line_loop(paddr, sz, cacheop);
468 __after_dc_op(cacheop);
471 #define __dc_entire_op(cacheop)
472 #define __dc_line_op(paddr, sz, cacheop)
473 #endif /* !CONFIG_SYS_DCACHE_OFF */
475 void invalidate_dcache_range(unsigned long start, unsigned long end)
480 #ifdef CONFIG_ISA_ARCV2
483 __dc_line_op(start, end - start, OP_INV);
485 #ifdef CONFIG_ISA_ARCV2
486 if (slc_exists && !ioc_exists)
487 __slc_rgn_op(start, end - start, OP_INV);
491 void flush_dcache_range(unsigned long start, unsigned long end)
496 #ifdef CONFIG_ISA_ARCV2
499 __dc_line_op(start, end - start, OP_FLUSH);
501 #ifdef CONFIG_ISA_ARCV2
502 if (slc_exists && !ioc_exists)
503 __slc_rgn_op(start, end - start, OP_FLUSH);
507 void flush_cache(unsigned long start, unsigned long size)
509 flush_dcache_range(start, start + size);
513 * As invalidate_dcache_all() is not used in generic U-Boot code and as we
514 * don't need it in arch/arc code alone (invalidate without flush) we implement
515 * flush_n_invalidate_dcache_all (flush and invalidate in 1 operation) because
516 * it's much safer. See [ NOTE 1 ] for more details.
518 void flush_n_invalidate_dcache_all(void)
520 __dc_entire_op(OP_FLUSH_N_INV);
522 #ifdef CONFIG_ISA_ARCV2
524 __slc_entire_op(OP_FLUSH_N_INV);
528 void flush_dcache_all(void)
530 __dc_entire_op(OP_FLUSH);
532 #ifdef CONFIG_ISA_ARCV2
534 __slc_entire_op(OP_FLUSH);