3 * Sascha Hauer, Pengutronix
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
30 #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
32 /* General purpose timers registers */
33 #define GPTCR __REG(TIMER_BASE) /* Control register */
34 #define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */
35 #define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */
36 #define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */
38 /* General purpose timers bitfields */
39 #define GPTCR_SWR (1 << 15) /* Software reset */
40 #define GPTCR_FRR (1 << 9) /* Freerun / restart */
41 #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
42 #define GPTCR_TEN 1 /* Timer enable */
44 DECLARE_GLOBAL_DATA_PTR;
47 * "time" is measured in 1 / CONFIG_SYS_HZ seconds,
48 * "tick" is internal timer period
51 #ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
52 /* ~0.4% error - measured with stop-watch on 100s boot-delay */
53 static inline unsigned long long tick_to_time(unsigned long long tick)
55 tick *= CONFIG_SYS_HZ;
56 do_div(tick, CONFIG_MX31_CLK32);
60 static inline unsigned long long time_to_tick(unsigned long long time)
62 time *= CONFIG_MX31_CLK32;
63 do_div(time, CONFIG_SYS_HZ);
67 static inline unsigned long long us_to_tick(unsigned long long us)
69 us = us * CONFIG_MX31_CLK32 + 999999;
75 #define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) \
77 #define US_PER_TICK (1000000 / CONFIG_MX31_CLK32)
79 static inline unsigned long long tick_to_time(unsigned long long tick)
81 do_div(tick, TICK_PER_TIME);
85 static inline unsigned long long time_to_tick(unsigned long long time)
87 return time * TICK_PER_TIME;
90 static inline unsigned long long us_to_tick(unsigned long long us)
92 us += US_PER_TICK - 1;
93 do_div(us, US_PER_TICK);
98 /* The 32768Hz 32-bit timer overruns in 131072 seconds */
103 /* setup GP Timer 1 */
105 for (i = 0; i < 100; i++)
106 GPTCR = 0; /* We have no udelay by now */
107 GPTPR = 0; /* 32Khz */
108 /* Freerun Mode, PERCLK1 input */
109 GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
114 unsigned long long get_ticks(void)
116 ulong now = GPTCNT; /* current tick value */
118 if (now >= gd->lastinc) /* normal mode (non roll) */
119 /* move stamp forward with absolut diff ticks */
120 gd->tbl += (now - gd->lastinc);
121 else /* we have rollover of incrementer */
122 gd->tbl += (0xFFFFFFFF - gd->lastinc) + now;
127 ulong get_timer_masked(void)
130 * get_ticks() returns a long long (64 bit), it wraps in
131 * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
132 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
133 * 5 * 10^6 days - long enough.
135 return tick_to_time(get_ticks());
138 ulong get_timer(ulong base)
140 return get_timer_masked() - base;
143 /* delay x useconds AND preserve advance timestamp value */
144 void __udelay(unsigned long usec)
146 unsigned long long tmp;
149 tmo = us_to_tick(usec);
150 tmp = get_ticks() + tmo; /* get current timestamp */
152 while (get_ticks() < tmp) /* loop till event */
157 * This function is derived from PowerPC code (timebase clock frequency).
158 * On ARM it returns the number of timer ticks per second.
160 ulong get_tbclk(void)
162 return CONFIG_MX31_CLK32;
165 void reset_cpu(ulong addr)
167 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
168 wdog->wcr = WDOG_ENABLE;
173 #ifdef CONFIG_HW_WATCHDOG
174 void mxc_hw_watchdog_enable(void)
176 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
180 * The timer watchdog can be set between
181 * 0.5 and 128 Seconds. If not defined
182 * in configuration file, sets 64 Seconds
184 #ifdef CONFIG_SYS_WD_TIMER_SECS
185 secs = (CONFIG_SYS_WD_TIMER_SECS << 1) & 0xFF;
190 setbits_le16(&wdog->wcr, (secs << WDOG_WT_SHIFT) | WDOG_ENABLE
195 void mxc_hw_watchdog_reset(void)
197 struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE;
199 writew(0x5555, &wdog->wsr);
200 writew(0xAAAA, &wdog->wsr);