2 * armboot - Startup Code for ARM1176 CPU-core
4 * Copyright (c) 2007 Samsung Electronics
7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
29 * jsgood (jsgood.yang@samsung.com)
30 * Base codes by scsuh (sc.suh)
33 #include <asm-offsets.h>
36 #ifdef CONFIG_ENABLE_MMU
37 #include <asm/proc/domain.h>
40 #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
41 #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
45 *************************************************************************
47 * Jump vector table as in table 3.1 in [1]
49 *************************************************************************
54 #ifndef CONFIG_NAND_SPL
55 ldr pc, _undefined_instruction
56 ldr pc, _software_interrupt
57 ldr pc, _prefetch_abort
63 _undefined_instruction:
64 .word undefined_instruction
66 .word software_interrupt
78 .word 0x12345678 /* now 16*4=64 */
85 .balignl 16,0xdeadbeef
87 *************************************************************************
89 * Startup Code (reset vector)
91 * do important init only if we don't start from memory!
92 * setup Memory and board specific bits prior to relocation.
93 * relocate armboot to ram
96 *************************************************************************
101 .word CONFIG_SYS_TEXT_BASE
104 * Below variable is very important because we use MMU in U-Boot.
105 * Without it, we cannot run code correctly before MMU is ON.
109 .word CONFIG_SYS_PHY_UBOOT_BASE
112 * These are defined in the board-specific linker script.
113 * Subtracting _start from them lets the linker put their
114 * relative position in the executable instead of leaving
118 .globl _bss_start_ofs
120 .word __bss_start - _start
124 .word __bss_end__ - _start
130 /* IRQ stack memory (calculated at run-time) + 8 bytes */
131 .globl IRQ_STACK_START_IN
136 * the actual reset code
141 * set the cpu to SVC32 mode
149 *************************************************************************
151 * CPU_init_critical registers
153 * setup important registers
154 * setup memory timing
156 *************************************************************************
159 * we do sys-critical inits only at reboot,
160 * not when booting from ram!
164 * When booting from NAND - it has definitely been a reset, so, no need
165 * to flush caches and disable the MMU
167 #ifndef CONFIG_NAND_SPL
169 * flush v4 I/D caches
172 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
173 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
176 * disable MMU stuff and caches
178 mrc p15, 0, r0, c1, c0, 0
179 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
180 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
181 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
182 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
184 /* Prepare to disable the MMU */
185 adr r2, mmu_disable_phys
186 sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - CONFIG_SYS_TEXT_BASE)
190 /* Run in a single cache-line */
192 mcr p15, 0, r0, c1, c0, 0
198 #ifdef CONFIG_DISABLE_TCM
202 mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */
208 mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/
210 mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/
215 #ifdef CONFIG_PERIPORT_REMAP
216 /* Peri port setup */
217 ldr r0, =CONFIG_PERIPORT_BASE
218 orr r0, r0, #CONFIG_PERIPORT_SIZE
219 mcr p15,0,r0,c15,c2,4
223 * Go setup Memory and board specific bits prior to relocation.
225 bl lowlevel_init /* go setup pll,mux,memory */
227 /* Set stackpointer in internal RAM to call board_init_f */
229 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
230 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
234 /*------------------------------------------------------------------------------*/
237 * void relocate_code (addr_sp, gd, addr_moni)
239 * This "function" does not return, instead it continues in RAM
240 * after relocating the monitor code.
245 mov r4, r0 /* save addr_sp */
246 mov r5, r1 /* save addr of gd */
247 mov r6, r2 /* save addr of destination */
249 /* Set up the stack */
255 beq clear_bss /* skip relocation */
256 mov r1, r6 /* r1 <- scratch for copy_loop */
257 ldr r3, _bss_start_ofs
258 add r2, r0, r3 /* r2 <- source end address */
261 ldmia r0!, {r9-r10} /* copy from source address [r0] */
262 stmia r1!, {r9-r10} /* copy to target address [r1] */
263 cmp r0, r2 /* until source end address [r2] */
266 #ifndef CONFIG_PRELOADER
268 * fix .rel.dyn relocations
270 ldr r0, _TEXT_BASE /* r0 <- Text base */
271 sub r9, r6, r0 /* r9 <- relocation offset */
272 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
273 add r10, r10, r0 /* r10 <- sym table in FLASH */
274 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
275 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
276 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
277 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
279 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
280 add r0, r0, r9 /* r0 <- location to fix up in RAM */
283 cmp r7, #23 /* relative fixup? */
285 cmp r7, #2 /* absolute fixup? */
287 /* ignore unknown type of fixup */
290 /* absolute fix: set location to (offset) symbol value */
291 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
292 add r1, r10, r1 /* r1 <- address of symbol in table */
293 ldr r1, [r1, #4] /* r1 <- symbol value */
294 add r1, r1, r9 /* r1 <- relocated sym addr */
297 /* relative fix: increase location by offset */
302 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
307 #ifdef CONFIG_ENABLE_MMU
309 /* enable domain access */
311 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
313 /* Set the TTB register */
314 ldr r0, _mmu_table_base
315 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
319 mcr p15, 0, r1, c2, c0, 0
322 mrc p15, 0, r0, c1, c0, 0
323 orr r0, r0, #1 /* Set CR_M to enable MMU */
325 /* Prepare to enable the MMU */
335 /* Run in a single cache-line */
338 mcr p15, 0, r0, c1, c0, 0
346 #ifndef CONFIG_PRELOADER
347 ldr r0, _bss_start_ofs
349 mov r4, r6 /* reloc addr */
352 mov r2, #0x00000000 /* clear */
354 clbss_l:str r2, [r0] /* clear loop... */
364 * We are done. Do not return, instead branch to second part of board
365 * initialization, now running from RAM.
367 #ifdef CONFIG_NAND_SPL
370 _nand_boot: .word nand_boot
372 ldr r0, _board_init_r_ofs
376 /* setup parameters for board_init_r */
377 mov r0, r5 /* gd_t */
378 mov r1, r6 /* dest_addr */
383 .word board_init_r - _start
387 .word __rel_dyn_start - _start
389 .word __rel_dyn_end - _start
391 .word __dynsym_start - _start
393 #ifdef CONFIG_ENABLE_MMU
398 #ifndef CONFIG_NAND_SPL
400 * we assume that cache operation is done before. (eg. cleanup_before_linux())
401 * actually, we don't need to do anything about cache if not use d-cache in
402 * U-Boot. So, in this function we clean only MMU. by scsuh
404 * void theLastJump(void *kernel, int arch_num, uint boot_params);
406 #ifdef CONFIG_ENABLE_MMU
411 ldr r4, _TEXT_PHY_BASE
412 adr r5, phy_last_jump
420 mrc p15, 0, r0, c1, c0, 0
421 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
422 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
423 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
424 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
425 mcr p15, 0, r0, c1, c0, 0
427 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
435 *************************************************************************
439 *************************************************************************
444 #define S_FRAME_SIZE 72
466 #define MODE_SVC 0x13
470 * use bad_save_user_regs for abort/prefetch/undef/swi ...
473 .macro bad_save_user_regs
474 /* carve out a frame on current user stack */
475 sub sp, sp, #S_FRAME_SIZE
476 /* Save user registers (now in svc mode) r0-r12 */
479 ldr r2, IRQ_STACK_START_IN
480 /* get values for "aborted" pc and cpsr (into parm regs) */
482 /* grab pointer to old stack */
483 add r0, sp, #S_FRAME_SIZE
487 /* save sp_SVC, lr_SVC, pc, cpsr */
489 /* save current stack into r0 (param register) */
494 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
496 /* save caller lr in position 0 of saved stack */
500 /* save spsr in position 1 of saved stack */
503 /* prepare SVC-Mode */
506 /* switch modes, make sure moves will execute */
508 /* capture return pc */
510 /* jump to next instruction & switch modes. */
514 .macro get_bad_stack_swi
515 /* space on current stack for scratch reg. */
517 /* save R0's value. */
519 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
520 /* save caller lr in position 0 of saved stack */
524 /* save spsr in position 1 of saved stack */
528 /* pop stack entry */
536 undefined_instruction:
539 bl do_undefined_instruction
545 bl do_software_interrupt
576 #endif /* CONFIG_NAND_SPL */