2 * armboot - Startup Code for S3C6400/ARM1176 CPU-core
4 * Copyright (c) 2007 Samsung Electronics
7 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * 2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)
28 * 2007-09-21 - Added MoviNAND and OneNAND boot codes by
29 * jsgood (jsgood.yang@samsung.com)
30 * Base codes by scsuh (sc.suh)
35 #ifdef CONFIG_ENABLE_MMU
36 #include <asm/proc/domain.h>
39 #include <asm/arch/s3c6400.h>
42 #if !defined(CONFIG_ENABLE_MMU) && !defined(CONFIG_SYS_PHY_UBOOT_BASE)
43 #define CONFIG_SYS_PHY_UBOOT_BASE CONFIG_SYS_UBOOT_BASE
47 *************************************************************************
49 * Jump vector table as in table 3.1 in [1]
51 *************************************************************************
56 #ifndef CONFIG_NAND_SPL
57 ldr pc, _undefined_instruction
58 ldr pc, _software_interrupt
59 ldr pc, _prefetch_abort
65 _undefined_instruction:
66 .word undefined_instruction
68 .word software_interrupt
80 .word 0x12345678 /* now 16*4=64 */
87 .balignl 16,0xdeadbeef
89 *************************************************************************
91 * Startup Code (reset vector)
93 * do important init only if we don't start from memory!
94 * setup Memory and board specific bits prior to relocation.
95 * relocate armboot to ram
98 *************************************************************************
105 * Below variable is very important because we use MMU in U-Boot.
106 * Without it, we cannot run code correctly before MMU is ON.
110 .word CONFIG_SYS_PHY_UBOOT_BASE
112 .globl _armboot_start
117 * These are defined in the board-specific linker script.
128 * the actual reset code
133 * set the cpu to SVC32 mode
141 *************************************************************************
143 * CPU_init_critical registers
145 * setup important registers
146 * setup memory timing
148 *************************************************************************
151 * we do sys-critical inits only at reboot,
152 * not when booting from ram!
156 * When booting from NAND - it has definitely been a reset, so, no need
157 * to flush caches and disable the MMU
159 #ifndef CONFIG_NAND_SPL
161 * flush v4 I/D caches
164 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
165 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
168 * disable MMU stuff and caches
170 mrc p15, 0, r0, c1, c0, 0
171 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
172 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
173 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
174 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
175 /* Prepare to disable the MMU */
176 adr r1, mmu_disable_phys
177 /* We presume we're within the first 1024 bytes */
179 ldr r2, _TEXT_PHY_BASE
186 /* Run in a single cache-line */
188 mcr p15, 0, r0, c1, c0, 0
195 #ifdef CONFIG_S3C64XX
196 /* Peri port setup */
199 mcr p15,0,r0,c15,c2,4 @ 256M (0x70000000 - 0x7fffffff)
203 * Go setup Memory and board specific bits prior to relocation.
205 bl lowlevel_init /* go setup pll,mux,memory */
208 #ifdef CONFIG_ENABLE_MMU
210 /* enable domain access */
212 mcr p15, 0, r5, c3, c0, 0 /* load domain access register */
214 /* Set the TTB register */
215 ldr r0, _mmu_table_base
216 ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE
220 mcr p15, 0, r1, c2, c0, 0
223 mrc p15, 0, r0, c1, c0, 0
224 orr r0, r0, #1 /* Set CR_M to enable MMU */
226 /* Prepare to enable the MMU */
236 /* Run in a single cache-line */
239 mcr p15, 0, r0, c1, c0, 0
246 /* Set up the stack */
248 ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */
249 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
250 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
251 sub sp, r0, #12 /* leave 3 words for abort-stack */
254 ldr r0, _bss_start /* find start of bss segment */
255 ldr r1, _bss_end /* stop here */
256 mov r2, #0 /* clear */
259 str r2, [r0] /* clear loop... */
264 #ifndef CONFIG_NAND_SPL
265 ldr pc, _start_armboot
274 #ifdef CONFIG_ENABLE_MMU
279 #ifndef CONFIG_NAND_SPL
281 * we assume that cache operation is done before. (eg. cleanup_before_linux())
282 * actually, we don't need to do anything about cache if not use d-cache in
283 * U-Boot. So, in this function we clean only MMU. by scsuh
285 * void theLastJump(void *kernel, int arch_num, uint boot_params);
287 #ifdef CONFIG_ENABLE_MMU
292 ldr r4, _TEXT_PHY_BASE
293 adr r5, phy_last_jump
301 mrc p15, 0, r0, c1, c0, 0
302 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
303 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
304 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
305 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
306 mcr p15, 0, r0, c1, c0, 0
308 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
314 *************************************************************************
318 *************************************************************************
323 #define S_FRAME_SIZE 72
345 #define MODE_SVC 0x13
349 * use bad_save_user_regs for abort/prefetch/undef/swi ...
352 .macro bad_save_user_regs
353 /* carve out a frame on current user stack */
354 sub sp, sp, #S_FRAME_SIZE
355 /* Save user registers (now in svc mode) r0-r12 */
358 ldr r2, _armboot_start
359 sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
360 /* set base 2 words into abort stack */
361 sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
362 /* get values for "aborted" pc and cpsr (into parm regs) */
364 /* grab pointer to old stack */
365 add r0, sp, #S_FRAME_SIZE
369 /* save sp_SVC, lr_SVC, pc, cpsr */
371 /* save current stack into r0 (param register) */
376 /* setup our mode stack (enter in banked mode) */
377 ldr r13, _armboot_start
378 /* move past malloc pool */
379 sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
380 /* move to reserved a couple spots for abort stack */
381 sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
383 /* save caller lr in position 0 of saved stack */
387 /* save spsr in position 1 of saved stack */
390 /* prepare SVC-Mode */
393 /* switch modes, make sure moves will execute */
395 /* capture return pc */
397 /* jump to next instruction & switch modes. */
401 .macro get_bad_stack_swi
402 /* space on current stack for scratch reg. */
404 /* save R0's value. */
406 /* get data regions start */
407 ldr r0, _armboot_start
408 /* move past malloc pool */
409 sub r0, r0, #(CONFIG_SYS_MALLOC_LEN)
410 /* move past gbl and a couple spots for abort stack */
411 sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)
412 /* save caller lr in position 0 of saved stack */
416 /* save spsr in position 1 of saved stack */
420 /* pop stack entry */
428 undefined_instruction:
431 bl do_undefined_instruction
437 bl do_software_interrupt
468 #endif /* CONFIG_NAND_SPL */