2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/hardware.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
47 .word 0xB4405F76 /* 2's complement of the checksum of the vectors */
54 _undefined_instruction: .word undefined_instruction
55 _software_interrupt: .word software_interrupt
56 _prefetch_abort: .word prefetch_abort
57 _data_abort: .word data_abort
58 _not_used: .word not_used
62 .balignl 16,0xdeadbeef
66 *************************************************************************
68 * Startup Code (reset vector)
70 * do important init only if we don't start from RAM!
71 * relocate armboot to ram
73 * jump to second stage
75 *************************************************************************
86 * These are defined in the board-specific linker script.
97 /* IRQ stack memory (calculated at run-time) */
98 .globl IRQ_STACK_START
102 /* IRQ stack memory (calculated at run-time) */
103 .globl FIQ_STACK_START
110 * the actual reset code
115 * set the cpu to SVC32 mode
123 * we do sys-critical inits only at reboot,
124 * not when booting from ram!
126 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
130 #ifdef CONFIG_LPC2292
134 #ifndef CONFIG_SKIP_RELOCATE_UBOOT
135 relocate: /* relocate U-Boot to RAM */
136 adr r0, _start /* r0 <- current position of code */
137 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
138 cmp r0, r1 /* don't reloc during debug */
142 #ifndef CONFIG_LPC2292 /* already done in lowlevel_init */
143 ldr r2, =0x0 /* Relocate the exception vectors */
144 cmp r1, r2 /* and associated data to address */
145 ldmneia r0!, {r3-r10} /* 0x0. Do nothing if TEXT_BASE is */
146 stmneia r2!, {r3-r10} /* 0x0. Copy the first 15 words. */
149 adrne r0, _start /* restore r0 */
150 #endif /* !CONFIG_LPC2292 */
153 ldr r2, _armboot_start
155 sub r2, r3, r2 /* r2 <- size of armboot */
156 add r2, r0, r2 /* r2 <- source end address */
159 ldmia r0!, {r3-r10} /* copy from source address [r0] */
160 stmia r1!, {r3-r10} /* copy to target address [r1] */
161 cmp r0, r2 /* until source end addreee [r2] */
164 #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
166 /* Set up the stack */
168 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
169 sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
170 sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
171 #ifdef CONFIG_USE_IRQ
172 sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
174 sub sp, r0, #12 /* leave 3 words for abort-stack */
175 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
178 ldr r0, _bss_start /* find start of bss segment */
179 ldr r1, _bss_end /* stop here */
180 mov r2, #0x00000000 /* clear */
182 clbss_l:str r2, [r0] /* clear loop... */
187 ldr pc, _start_armboot
189 _start_armboot: .word start_armboot
192 *************************************************************************
194 * CPU_init_critical registers
196 * setup important registers
197 * setup memory timing
199 *************************************************************************
202 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
204 /* Interupt-Controller base addresses */
205 INTMR1: .word 0x80000280 @ 32 bit size
206 INTMR2: .word 0x80001280 @ 16 bit size
207 INTMR3: .word 0x80002280 @ 8 bit size
210 SYSCON1: .word 0x80000100
211 SYSCON2: .word 0x80001100
212 SYSCON3: .word 0x80002200
214 #define CLKCTL 0x6 /* mask */
215 #define CLKCTL_18 0x0 /* 18.432 MHz */
216 #define CLKCTL_36 0x2 /* 36.864 MHz */
217 #define CLKCTL_49 0x4 /* 49.152 MHz */
218 #define CLKCTL_73 0x6 /* 73.728 MHz */
220 #elif defined(CONFIG_LPC2292)
221 PLLCFG_ADR: .word PLLCFG
222 PLLFEED_ADR: .word PLLFEED
223 PLLCON_ADR: .word PLLCON
224 PLLSTAT_ADR: .word PLLSTAT
225 VPBDIV_ADR: .word VPBDIV
226 MEMMAP_ADR: .word MEMMAP
231 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
234 * mask all IRQs by clearing all bits in the INTMRs
245 * flush v4 I/D caches
248 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
249 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
252 * disable MMU stuff and caches
255 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
256 bic r0, r0, #0x0000008f @ clear bits 7, 3:0 (B--- WCAM)
257 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
259 #elif defined(CONFIG_NETARM)
261 * prior to software reset : need to set pin PORTC4 to be *HRESET
263 ldr r0, =NETARM_GEN_MODULE_BASE
264 ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
265 NETARM_GEN_PORT_DIR(0x10))
266 str r1, [r0, #+NETARM_GEN_PORTC]
268 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
269 * for an explanation of this process
271 ldr r0, =NETARM_GEN_MODULE_BASE
272 ldr r1, =NETARM_GEN_SW_SVC_RESETA
273 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
274 ldr r1, =NETARM_GEN_SW_SVC_RESETB
275 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
276 ldr r1, =NETARM_GEN_SW_SVC_RESETA
277 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
278 ldr r1, =NETARM_GEN_SW_SVC_RESETB
279 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
281 * setup PLL and System Config
283 ldr r0, =NETARM_GEN_MODULE_BASE
285 ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
286 NETARM_GEN_SYS_CFG_BUSFULL | \
287 NETARM_GEN_SYS_CFG_USER_EN | \
288 NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
289 NETARM_GEN_SYS_CFG_BUSARB_INT | \
290 NETARM_GEN_SYS_CFG_BUSMON_EN )
292 str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
294 #ifndef CONFIG_NETARM_PLL_BYPASS
295 ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
296 NETARM_GEN_PLL_CTL_POLTST_DEF | \
297 NETARM_GEN_PLL_CTL_INDIV(1) | \
298 NETARM_GEN_PLL_CTL_ICP_DEF | \
299 NETARM_GEN_PLL_CTL_OUTDIV(2) )
300 str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
304 * mask all IRQs by clearing all bits in the INTMRs
307 ldr r0, =NETARM_GEN_MODULE_BASE
308 str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
310 #elif defined(CONFIG_S3C4510B)
313 * Mask off all IRQ sources
323 ldr r1, =0x83ffffa0 /* cache-disabled */
326 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
327 /* No specific initialisation for IntegratorAP/CM720T as yet */
328 #elif defined(CONFIG_LPC2292)
332 /* First disconnect and disable the PLL */
336 ldr r0, PLLFEED_ADR /* start feed sequence */
338 str r4, [r0] /* feed sequence done */
339 /* Set new M and P values */
341 mov r1, #0x23 /* M=4 and P=2 */
343 ldr r0, PLLFEED_ADR /* start feed sequence */
345 str r4, [r0] /* feed sequence done */
346 /* Then enable the PLL */
348 mov r1, #0x01 /* PLL enable bit */
350 ldr r0, PLLFEED_ADR /* start feed sequence */
352 str r4, [r0] /* feed sequence done */
353 /* Wait for the lock */
355 mov r1, #0x400 /* lock bit */
361 /* And finally connect the PLL */
363 mov r1, #0x03 /* PLL enable bit and connect bit */
365 ldr r0, PLLFEED_ADR /* start feed sequence */
367 str r4, [r0] /* feed sequence done */
368 /* Set-up VPBDIV register */
370 mov r1, #0x01 /* VPB clock is same as process clock */
373 #error No cpu_init_crit() defined for current CPU type
376 #ifdef CONFIG_ARM7_REVD
377 /* set clock speed */
378 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
379 /* !!! not doing DRAM refresh properly! */
383 orr r1, r1, #CLKCTL_36
387 #ifndef CONFIG_LPC2292
390 * before relocating, we have to setup RAM timing
391 * because memory timing is board-dependent, you will
392 * find a lowlevel_init.S in your board directory.
402 *************************************************************************
406 *************************************************************************
412 #define S_FRAME_SIZE 72
434 #define MODE_SVC 0x13
438 * use bad_save_user_regs for abort/prefetch/undef/swi ...
439 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
442 .macro bad_save_user_regs
443 sub sp, sp, #S_FRAME_SIZE
444 stmia sp, {r0 - r12} @ Calling r0-r12
447 ldr r2, _armboot_start
448 sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
449 sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
450 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
451 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
455 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
459 .macro irq_save_user_regs
460 sub sp, sp, #S_FRAME_SIZE
461 stmia sp, {r0 - r12} @ Calling r0-r12
463 stmdb r8, {sp, lr}^ @ Calling SP, LR
464 str lr, [r8, #0] @ Save calling PC
466 str r6, [r8, #4] @ Save CPSR
467 str r0, [r8, #8] @ Save OLD_R0
471 .macro irq_restore_user_regs
472 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
474 ldr lr, [sp, #S_PC] @ Get PC
475 add sp, sp, #S_FRAME_SIZE
476 subs pc, lr, #4 @ return & move spsr_svc into cpsr
480 ldr r13, _armboot_start @ setup our mode stack
481 sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
482 sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
484 str lr, [r13] @ save caller lr / spsr
488 mov r13, #MODE_SVC @ prepare SVC-Mode
494 .macro get_irq_stack @ setup IRQ stack
495 ldr sp, IRQ_STACK_START
498 .macro get_fiq_stack @ setup FIQ stack
499 ldr sp, FIQ_STACK_START
506 undefined_instruction:
509 bl do_undefined_instruction
515 bl do_software_interrupt
535 #ifdef CONFIG_USE_IRQ
542 irq_restore_user_regs
547 /* someone ought to write a more effiction fiq_save_user_regs */
550 irq_restore_user_regs
568 #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO)
573 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
574 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
575 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
576 bic ip, ip, #0x000f @ ............wcam
577 bic ip, ip, #0x2100 @ ..v....s........
578 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
580 #elif defined(CONFIG_NETARM)
584 ldr r1, =NETARM_MEM_MODULE_BASE
585 ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
588 ldr r1, =(relocate-TEXT_BASE)
590 ldr r4, =NETARM_GEN_MODULE_BASE
591 ldr r1, =NETARM_GEN_SW_SVC_RESETA
592 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
593 ldr r1, =NETARM_GEN_SW_SVC_RESETB
594 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
595 ldr r1, =NETARM_GEN_SW_SVC_RESETA
596 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
597 ldr r1, =NETARM_GEN_SW_SVC_RESETB
598 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
600 #elif defined(CONFIG_S3C4510B)
601 /* Nothing done here as reseting the CPU is board specific, depending
602 * on external peripherals such as watchdog timers, etc. */
603 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
604 /* No specific reset actions for IntegratorAP/CM720T as yet */
605 #elif defined(CONFIG_LPC2292)
611 #error No reset_cpu() defined for current CPU type