2 * armboot - Startup Code for ARM720 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm-offsets.h>
29 #include <asm/hardware.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
47 .word 0xB4405F76 /* 2's complement of the checksum of the vectors */
54 #ifdef CONFIG_SPL_BUILD
55 _undefined_instruction: .word _undefined_instruction
56 _software_interrupt: .word _software_interrupt
57 _prefetch_abort: .word _prefetch_abort
58 _data_abort: .word _data_abort
59 _not_used: .word _not_used
63 _undefined_instruction: .word undefined_instruction
64 _software_interrupt: .word software_interrupt
65 _prefetch_abort: .word prefetch_abort
66 _data_abort: .word data_abort
67 _not_used: .word not_used
70 #endif /* CONFIG_SPL_BUILD */
72 .balignl 16,0xdeadbeef
76 *************************************************************************
78 * Startup Code (reset vector)
80 * do important init only if we don't start from RAM!
81 * relocate armboot to ram
83 * jump to second stage
85 *************************************************************************
90 .word CONFIG_SYS_TEXT_BASE
93 * These are defined in the board-specific linker script.
94 * Subtracting _start from them lets the linker put their
95 * relative position in the executable instead of leaving
100 .word __bss_start - _start
104 .word __bss_end__ - _start
110 #ifdef CONFIG_USE_IRQ
111 /* IRQ stack memory (calculated at run-time) */
112 .globl IRQ_STACK_START
116 /* IRQ stack memory (calculated at run-time) */
117 .globl FIQ_STACK_START
122 /* IRQ stack memory (calculated at run-time) + 8 bytes */
123 .globl IRQ_STACK_START_IN
128 * the actual reset code
133 * set the cpu to SVC32 mode
141 * we do sys-critical inits only at reboot,
142 * not when booting from ram!
144 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
148 #ifdef CONFIG_LPC2292
152 /* Set stackpointer in internal RAM to call board_init_f */
154 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
155 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
159 /*------------------------------------------------------------------------------*/
162 * void relocate_code (addr_sp, gd, addr_moni)
164 * This "function" does not return, instead it continues in RAM
165 * after relocating the monitor code.
170 mov r4, r0 /* save addr_sp */
171 mov r5, r1 /* save addr of gd */
172 mov r6, r2 /* save addr of destination */
174 /* Set up the stack */
180 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
181 beq clear_bss /* skip relocation */
182 mov r1, r6 /* r1 <- scratch for copy_loop */
183 ldr r3, _bss_start_ofs
184 add r2, r0, r3 /* r2 <- source end address */
187 ldmia r0!, {r9-r10} /* copy from source address [r0] */
188 stmia r1!, {r9-r10} /* copy to target address [r1] */
189 cmp r0, r2 /* until source end address [r2] */
192 #ifndef CONFIG_SPL_BUILD
194 * fix .rel.dyn relocations
196 ldr r0, _TEXT_BASE /* r0 <- Text base */
197 sub r9, r6, r0 /* r9 <- relocation offset */
198 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
199 add r10, r10, r0 /* r10 <- sym table in FLASH */
200 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
201 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
202 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
203 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
205 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
206 add r0, r0, r9 /* r0 <- location to fix up in RAM */
209 cmp r7, #23 /* relative fixup? */
211 cmp r7, #2 /* absolute fixup? */
213 /* ignore unknown type of fixup */
216 /* absolute fix: set location to (offset) symbol value */
217 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
218 add r1, r10, r1 /* r1 <- address of symbol in table */
219 ldr r1, [r1, #4] /* r1 <- symbol value */
220 add r1, r1, r9 /* r1 <- relocated sym addr */
223 /* relative fix: increase location by offset */
228 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
234 #ifndef CONFIG_SPL_BUILD
235 ldr r0, _bss_start_ofs
237 mov r4, r6 /* reloc addr */
240 mov r2, #0x00000000 /* clear */
242 clbss_l:cmp r0, r1 /* clear loop... */
243 bhs clbss_e /* if reached end of bss, exit */
254 * We are done. Do not return, instead branch to second part of board
255 * initialization, now running from RAM.
257 ldr r0, _board_init_r_ofs
261 /* setup parameters for board_init_r */
262 mov r0, r5 /* gd_t */
263 mov r1, r6 /* dest_addr */
268 .word board_init_r - _start
271 .word __rel_dyn_start - _start
273 .word __rel_dyn_end - _start
275 .word __dynsym_start - _start
278 *************************************************************************
280 * CPU_init_critical registers
282 * setup important registers
283 * setup memory timing
285 *************************************************************************
288 #if defined(CONFIG_LPC2292)
289 PLLCFG_ADR: .word PLLCFG
290 PLLFEED_ADR: .word PLLFEED
291 PLLCON_ADR: .word PLLCON
292 PLLSTAT_ADR: .word PLLSTAT
293 VPBDIV_ADR: .word VPBDIV
294 MEMMAP_ADR: .word MEMMAP
299 #if defined(CONFIG_NETARM)
301 * prior to software reset : need to set pin PORTC4 to be *HRESET
303 ldr r0, =NETARM_GEN_MODULE_BASE
304 ldr r1, =(NETARM_GEN_PORT_MODE(0x10) | \
305 NETARM_GEN_PORT_DIR(0x10))
306 str r1, [r0, #+NETARM_GEN_PORTC]
308 * software reset : see HW Ref. Guide 8.2.4 : Software Service register
309 * for an explanation of this process
311 ldr r0, =NETARM_GEN_MODULE_BASE
312 ldr r1, =NETARM_GEN_SW_SVC_RESETA
313 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
314 ldr r1, =NETARM_GEN_SW_SVC_RESETB
315 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
316 ldr r1, =NETARM_GEN_SW_SVC_RESETA
317 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
318 ldr r1, =NETARM_GEN_SW_SVC_RESETB
319 str r1, [r0, #+NETARM_GEN_SOFTWARE_SERVICE]
321 * setup PLL and System Config
323 ldr r0, =NETARM_GEN_MODULE_BASE
325 ldr r1, =( NETARM_GEN_SYS_CFG_LENDIAN | \
326 NETARM_GEN_SYS_CFG_BUSFULL | \
327 NETARM_GEN_SYS_CFG_USER_EN | \
328 NETARM_GEN_SYS_CFG_ALIGN_ABORT | \
329 NETARM_GEN_SYS_CFG_BUSARB_INT | \
330 NETARM_GEN_SYS_CFG_BUSMON_EN )
332 str r1, [r0, #+NETARM_GEN_SYSTEM_CONTROL]
334 #ifndef CONFIG_NETARM_PLL_BYPASS
335 ldr r1, =( NETARM_GEN_PLL_CTL_PLLCNT(NETARM_PLL_COUNT_VAL) | \
336 NETARM_GEN_PLL_CTL_POLTST_DEF | \
337 NETARM_GEN_PLL_CTL_INDIV(1) | \
338 NETARM_GEN_PLL_CTL_ICP_DEF | \
339 NETARM_GEN_PLL_CTL_OUTDIV(2) )
340 str r1, [r0, #+NETARM_GEN_PLL_CONTROL]
344 * mask all IRQs by clearing all bits in the INTMRs
347 ldr r0, =NETARM_GEN_MODULE_BASE
348 str r1, [r0, #+NETARM_GEN_INTR_ENABLE]
350 #elif defined(CONFIG_S3C4510B)
353 * Mask off all IRQ sources
363 ldr r1, =0x83ffffa0 /* cache-disabled */
366 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
367 /* No specific initialisation for IntegratorAP/CM720T as yet */
368 #elif defined(CONFIG_LPC2292)
372 /* First disconnect and disable the PLL */
376 ldr r0, PLLFEED_ADR /* start feed sequence */
378 str r4, [r0] /* feed sequence done */
379 /* Set new M and P values */
381 mov r1, #0x23 /* M=4 and P=2 */
383 ldr r0, PLLFEED_ADR /* start feed sequence */
385 str r4, [r0] /* feed sequence done */
386 /* Then enable the PLL */
388 mov r1, #0x01 /* PLL enable bit */
390 ldr r0, PLLFEED_ADR /* start feed sequence */
392 str r4, [r0] /* feed sequence done */
393 /* Wait for the lock */
395 mov r1, #0x400 /* lock bit */
401 /* And finally connect the PLL */
403 mov r1, #0x03 /* PLL enable bit and connect bit */
405 ldr r0, PLLFEED_ADR /* start feed sequence */
407 str r4, [r0] /* feed sequence done */
408 /* Set-up VPBDIV register */
410 mov r1, #0x01 /* VPB clock is same as process clock */
413 #error No cpu_init_crit() defined for current CPU type
416 #ifdef CONFIG_ARM7_REVD
417 /* set clock speed */
418 /* !!! we run @ 36 MHz due to a hardware flaw in Rev. D processors */
419 /* !!! not doing DRAM refresh properly! */
423 orr r1, r1, #CLKCTL_36
427 #ifndef CONFIG_LPC2292
430 * before relocating, we have to setup RAM timing
431 * because memory timing is board-dependent, you will
432 * find a lowlevel_init.S in your board directory.
441 #ifndef CONFIG_SPL_BUILD
443 *************************************************************************
447 *************************************************************************
453 #define S_FRAME_SIZE 72
475 #define MODE_SVC 0x13
479 * use bad_save_user_regs for abort/prefetch/undef/swi ...
480 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
483 .macro bad_save_user_regs
484 sub sp, sp, #S_FRAME_SIZE
485 stmia sp, {r0 - r12} @ Calling r0-r12
488 ldr r2, IRQ_STACK_START_IN
489 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
490 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
494 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
498 .macro irq_save_user_regs
499 sub sp, sp, #S_FRAME_SIZE
500 stmia sp, {r0 - r12} @ Calling r0-r12
502 stmdb r8, {sp, lr}^ @ Calling SP, LR
503 str lr, [r8, #0] @ Save calling PC
505 str r6, [r8, #4] @ Save CPSR
506 str r0, [r8, #8] @ Save OLD_R0
510 .macro irq_restore_user_regs
511 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
513 ldr lr, [sp, #S_PC] @ Get PC
514 add sp, sp, #S_FRAME_SIZE
515 subs pc, lr, #4 @ return & move spsr_svc into cpsr
519 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
521 str lr, [r13] @ save caller lr / spsr
525 mov r13, #MODE_SVC @ prepare SVC-Mode
531 .macro get_irq_stack @ setup IRQ stack
532 ldr sp, IRQ_STACK_START
535 .macro get_fiq_stack @ setup FIQ stack
536 ldr sp, FIQ_STACK_START
543 undefined_instruction:
546 bl do_undefined_instruction
552 bl do_software_interrupt
572 #ifdef CONFIG_USE_IRQ
579 irq_restore_user_regs
584 /* someone ought to write a more effiction fiq_save_user_regs */
587 irq_restore_user_regs
604 #endif /* CONFIG_SPL_BUILD */
606 #if defined(CONFIG_NETARM)
610 ldr r1, =NETARM_MEM_MODULE_BASE
611 ldr r0, [r1, #+NETARM_MEM_CS0_BASE_ADDR]
614 ldr r1, =(relocate-CONFIG_SYS_TEXT_BASE)
616 ldr r4, =NETARM_GEN_MODULE_BASE
617 ldr r1, =NETARM_GEN_SW_SVC_RESETA
618 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
619 ldr r1, =NETARM_GEN_SW_SVC_RESETB
620 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
621 ldr r1, =NETARM_GEN_SW_SVC_RESETA
622 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
623 ldr r1, =NETARM_GEN_SW_SVC_RESETB
624 str r1, [r4, #+NETARM_GEN_SOFTWARE_SERVICE]
626 #elif defined(CONFIG_S3C4510B)
627 /* Nothing done here as reseting the CPU is board specific, depending
628 * on external peripherals such as watchdog timers, etc. */
629 #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
630 /* No specific reset actions for IntegratorAP/CM720T as yet */
631 #elif defined(CONFIG_LPC2292)
637 #error No reset_cpu() defined for current CPU type