2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm-offsets.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (called from the ARM reset exception vector)
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
76 .word CONFIG_SYS_TEXT_BASE
79 * These are defined in the board-specific linker script.
80 * Subtracting _start from them lets the linker put their
81 * relative position in the executable instead of leaving
86 .word __bss_start - _start
93 /* IRQ stack memory (calculated at run-time) */
94 .globl IRQ_STACK_START
98 /* IRQ stack memory (calculated at run-time) */
99 .globl FIQ_STACK_START
104 /* IRQ stack memory (calculated at run-time) + 8 bytes */
105 .globl IRQ_STACK_START_IN
110 * the actual start code
115 * set the cpu to SVC32 mode
125 #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
127 * relocate exception table
139 #ifdef CONFIG_S3C24X0
140 /* turn off the watchdog */
142 # if defined(CONFIG_S3C2400)
143 # define pWTCON 0x15300000
144 # define INTMSK 0x14400008 /* Interupt-Controller base addresses */
145 # define CLKDIVN 0x14800014 /* clock divisor register */
147 # define pWTCON 0x53000000
148 # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
149 # define INTSUBMSK 0x4A00001C
150 # define CLKDIVN 0x4C000014 /* clock divisor register */
158 * mask all IRQs by setting all bits in the INTMR - default
163 # if defined(CONFIG_S3C2410)
169 /* FCLK:HCLK:PCLK = 1:2:4 */
170 /* default FCLK is 120 MHz ! */
174 #endif /* CONFIG_S3C24X0 */
177 * we do sys-critical inits only at reboot,
178 * not when booting from ram!
180 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
184 /* Set stackpointer in internal RAM to call board_init_f */
186 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
190 /*------------------------------------------------------------------------------*/
193 * void relocate_code (addr_sp, gd, addr_moni)
195 * This "function" does not return, instead it continues in RAM
196 * after relocating the monitor code.
201 mov r4, r0 /* save addr_sp */
202 mov r5, r1 /* save addr of gd */
203 mov r6, r2 /* save addr of destination */
204 mov r7, r2 /* save addr of destination */
206 /* Set up the stack */
212 ldr r3, _bss_start_ofs
213 add r2, r0, r3 /* r2 <- source end address */
218 ldmia r0!, {r9-r10} /* copy from source address [r0] */
219 stmia r6!, {r9-r10} /* copy to target address [r1] */
220 cmp r0, r2 /* until source end address [r2] */
223 #ifndef CONFIG_PRELOADER
225 * fix .rel.dyn relocations
227 ldr r0, _TEXT_BASE /* r0 <- Text base */
228 sub r9, r7, r0 /* r9 <- relocation offset */
229 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
230 add r10, r10, r0 /* r10 <- sym table in FLASH */
231 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
232 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
233 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
234 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
236 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
237 add r0, r0, r9 /* r0 <- location to fix up in RAM */
240 cmp r8, #23 /* relative fixup? */
242 cmp r8, #2 /* absolute fixup? */
244 /* ignore unknown type of fixup */
247 /* absolute fix: set location to (offset) symbol value */
248 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
249 add r1, r10, r1 /* r1 <- address of symbol in table */
250 ldr r1, [r1, #4] /* r1 <- symbol value */
251 add r1, r9 /* r1 <- relocated sym addr */
254 /* relative fix: increase location by offset */
259 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
265 #ifndef CONFIG_PRELOADER
266 ldr r0, _bss_start_ofs
268 ldr r3, _TEXT_BASE /* Text base */
269 mov r4, r7 /* reloc addr */
272 mov r2, #0x00000000 /* clear */
274 clbss_l:str r2, [r0] /* clear loop... */
284 * We are done. Do not return, instead branch to second part of board
285 * initialization, now running from RAM.
287 #ifdef CONFIG_NAND_SPL
288 ldr r0, _nand_boot_ofs
294 ldr r0, _board_init_r_ofs
298 /* setup parameters for board_init_r */
299 mov r0, r5 /* gd_t */
300 mov r1, r7 /* dest_addr */
305 .word board_init_r - _start
309 .word __rel_dyn_start - _start
311 .word __rel_dyn_end - _start
313 .word __dynsym_start - _start
316 *************************************************************************
318 * CPU_init_critical registers
320 * setup important registers
321 * setup memory timing
323 *************************************************************************
327 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
330 * flush v4 I/D caches
333 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
334 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
337 * disable MMU stuff and caches
339 mrc p15, 0, r0, c1, c0, 0
340 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
341 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
342 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
343 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
344 mcr p15, 0, r0, c1, c0, 0
347 * before relocating, we have to setup RAM timing
348 * because memory timing is board-dependend, you will
349 * find a lowlevel_init.S in your board directory.
357 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
360 *************************************************************************
364 *************************************************************************
370 #define S_FRAME_SIZE 72
392 #define MODE_SVC 0x13
396 * use bad_save_user_regs for abort/prefetch/undef/swi ...
397 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
400 .macro bad_save_user_regs
401 sub sp, sp, #S_FRAME_SIZE
402 stmia sp, {r0 - r12} @ Calling r0-r12
403 ldr r2, IRQ_STACK_START_IN
404 ldmia r2, {r2 - r3} @ get pc, cpsr
405 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
409 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
413 .macro irq_save_user_regs
414 sub sp, sp, #S_FRAME_SIZE
415 stmia sp, {r0 - r12} @ Calling r0-r12
417 stmdb r7, {sp, lr}^ @ Calling SP, LR
418 str lr, [r7, #0] @ Save calling PC
420 str r6, [r7, #4] @ Save CPSR
421 str r0, [r7, #8] @ Save OLD_R0
425 .macro irq_restore_user_regs
426 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
428 ldr lr, [sp, #S_PC] @ Get PC
429 add sp, sp, #S_FRAME_SIZE
430 /* return & move spsr_svc into cpsr */
435 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
437 str lr, [r13] @ save caller lr / spsr
441 mov r13, #MODE_SVC @ prepare SVC-Mode
448 .macro get_irq_stack @ setup IRQ stack
449 ldr sp, IRQ_STACK_START
452 .macro get_fiq_stack @ setup FIQ stack
453 ldr sp, FIQ_STACK_START
460 undefined_instruction:
463 bl do_undefined_instruction
469 bl do_software_interrupt
489 #ifdef CONFIG_USE_IRQ
496 irq_restore_user_regs
501 /* someone ought to write a more effiction fiq_save_user_regs */
504 irq_restore_user_regs