2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm-offsets.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (called from the ARM reset exception vector)
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
76 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
77 .word CONFIG_SPL_TEXT_BASE
79 .word CONFIG_SYS_TEXT_BASE
83 * These are defined in the board-specific linker script.
84 * Subtracting _start from them lets the linker put their
85 * relative position in the executable instead of leaving
90 .word __bss_start - _start
94 .word __bss_end - _start
100 #ifdef CONFIG_USE_IRQ
101 /* IRQ stack memory (calculated at run-time) */
102 .globl IRQ_STACK_START
106 /* IRQ stack memory (calculated at run-time) */
107 .globl FIQ_STACK_START
112 /* IRQ stack memory (calculated at run-time) + 8 bytes */
113 .globl IRQ_STACK_START_IN
118 * the actual start code
123 * set the cpu to SVC32 mode
130 #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
132 * relocate exception table
144 #ifdef CONFIG_S3C24X0
145 /* turn off the watchdog */
147 # if defined(CONFIG_S3C2400)
148 # define pWTCON 0x15300000
149 # define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
150 # define CLKDIVN 0x14800014 /* clock divisor register */
152 # define pWTCON 0x53000000
153 # define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
154 # define INTSUBMSK 0x4A00001C
155 # define CLKDIVN 0x4C000014 /* clock divisor register */
163 * mask all IRQs by setting all bits in the INTMR - default
168 # if defined(CONFIG_S3C2410)
174 /* FCLK:HCLK:PCLK = 1:2:4 */
175 /* default FCLK is 120 MHz ! */
179 #endif /* CONFIG_S3C24X0 */
182 * we do sys-critical inits only at reboot,
183 * not when booting from ram!
185 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
191 /*------------------------------------------------------------------------------*/
194 * void relocate_code (addr_sp, gd, addr_moni)
196 * This function relocates the monitor code.
200 mov r4, r0 /* save addr_sp */
201 mov r5, r1 /* save addr of gd */
202 mov r6, r2 /* save addr of destination */
206 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
207 beq relocate_done /* skip relocation */
208 mov r1, r6 /* r1 <- scratch for copy_loop */
209 ldr r3, _bss_start_ofs
210 add r2, r0, r3 /* r2 <- source end address */
213 ldmia r0!, {r9-r10} /* copy from source address [r0] */
214 stmia r1!, {r9-r10} /* copy to target address [r1] */
215 cmp r0, r2 /* until source end address [r2] */
218 #ifndef CONFIG_SPL_BUILD
220 * fix .rel.dyn relocations
222 ldr r0, _TEXT_BASE /* r0 <- Text base */
223 sub r9, r6, r0 /* r9 <- relocation offset */
224 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
225 add r10, r10, r0 /* r10 <- sym table in FLASH */
226 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
227 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
228 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
229 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
231 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
232 add r0, r0, r9 /* r0 <- location to fix up in RAM */
235 cmp r7, #23 /* relative fixup? */
237 cmp r7, #2 /* absolute fixup? */
239 /* ignore unknown type of fixup */
242 /* absolute fix: set location to (offset) symbol value */
243 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
244 add r1, r10, r1 /* r1 <- address of symbol in table */
245 ldr r1, [r1, #4] /* r1 <- symbol value */
246 add r1, r1, r9 /* r1 <- relocated sym addr */
249 /* relative fix: increase location by offset */
254 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
264 .word __rel_dyn_start - _start
266 .word __rel_dyn_end - _start
268 .word __dynsym_start - _start
270 .globl c_runtime_cpu_setup
276 *************************************************************************
278 * CPU_init_critical registers
280 * setup important registers
281 * setup memory timing
283 *************************************************************************
287 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
290 * flush v4 I/D caches
293 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
294 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
297 * disable MMU stuff and caches
299 mrc p15, 0, r0, c1, c0, 0
300 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
301 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
302 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
303 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
304 mcr p15, 0, r0, c1, c0, 0
307 * before relocating, we have to setup RAM timing
308 * because memory timing is board-dependend, you will
309 * find a lowlevel_init.S in your board directory.
317 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
320 *************************************************************************
324 *************************************************************************
330 #define S_FRAME_SIZE 72
352 #define MODE_SVC 0x13
356 * use bad_save_user_regs for abort/prefetch/undef/swi ...
357 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
360 .macro bad_save_user_regs
361 sub sp, sp, #S_FRAME_SIZE
362 stmia sp, {r0 - r12} @ Calling r0-r12
363 ldr r2, IRQ_STACK_START_IN
364 ldmia r2, {r2 - r3} @ get pc, cpsr
365 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
369 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
373 .macro irq_save_user_regs
374 sub sp, sp, #S_FRAME_SIZE
375 stmia sp, {r0 - r12} @ Calling r0-r12
377 stmdb r7, {sp, lr}^ @ Calling SP, LR
378 str lr, [r7, #0] @ Save calling PC
380 str r6, [r7, #4] @ Save CPSR
381 str r0, [r7, #8] @ Save OLD_R0
385 .macro irq_restore_user_regs
386 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
388 ldr lr, [sp, #S_PC] @ Get PC
389 add sp, sp, #S_FRAME_SIZE
390 /* return & move spsr_svc into cpsr */
395 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
397 str lr, [r13] @ save caller lr / spsr
401 mov r13, #MODE_SVC @ prepare SVC-Mode
408 .macro get_irq_stack @ setup IRQ stack
409 ldr sp, IRQ_STACK_START
412 .macro get_fiq_stack @ setup FIQ stack
413 ldr sp, FIQ_STACK_START
420 undefined_instruction:
423 bl do_undefined_instruction
429 bl do_software_interrupt
449 #ifdef CONFIG_USE_IRQ
456 irq_restore_user_regs
461 /* someone ought to write a more effiction fiq_save_user_regs */
464 irq_restore_user_regs