2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
8 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm-offsets.h>
16 *************************************************************************
18 * Jump vector table as in table 3.1 in [1]
20 *************************************************************************
26 ldr pc, _undefined_instruction
27 ldr pc, _software_interrupt
28 ldr pc, _prefetch_abort
34 _undefined_instruction: .word undefined_instruction
35 _software_interrupt: .word software_interrupt
36 _prefetch_abort: .word prefetch_abort
37 _data_abort: .word data_abort
38 _not_used: .word not_used
42 .balignl 16,0xdeadbeef
46 *************************************************************************
48 * Startup Code (called from the ARM reset exception vector)
50 * do important init only if we don't start from memory!
51 * relocate armboot to ram
53 * jump to second stage
55 *************************************************************************
59 /* IRQ stack memory (calculated at run-time) */
60 .globl IRQ_STACK_START
64 /* IRQ stack memory (calculated at run-time) */
65 .globl FIQ_STACK_START
70 /* IRQ stack memory (calculated at run-time) + 8 bytes */
71 .globl IRQ_STACK_START_IN
76 * the actual start code
81 * set the cpu to SVC32 mode
88 #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
90 * relocate exception table
102 #ifdef CONFIG_S3C24X0
103 /* turn off the watchdog */
105 # if defined(CONFIG_S3C2400)
106 # define pWTCON 0x15300000
107 # define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
108 # define CLKDIVN 0x14800014 /* clock divisor register */
110 # define pWTCON 0x53000000
111 # define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
112 # define INTSUBMSK 0x4A00001C
113 # define CLKDIVN 0x4C000014 /* clock divisor register */
121 * mask all IRQs by setting all bits in the INTMR - default
126 # if defined(CONFIG_S3C2410)
132 /* FCLK:HCLK:PCLK = 1:2:4 */
133 /* default FCLK is 120 MHz ! */
137 #endif /* CONFIG_S3C24X0 */
140 * we do sys-critical inits only at reboot,
141 * not when booting from ram!
143 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
149 /*------------------------------------------------------------------------------*/
151 .globl c_runtime_cpu_setup
157 *************************************************************************
159 * CPU_init_critical registers
161 * setup important registers
162 * setup memory timing
164 *************************************************************************
168 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
171 * flush v4 I/D caches
174 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
175 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
178 * disable MMU stuff and caches
180 mrc p15, 0, r0, c1, c0, 0
181 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
182 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
183 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
184 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
185 mcr p15, 0, r0, c1, c0, 0
188 * before relocating, we have to setup RAM timing
189 * because memory timing is board-dependend, you will
190 * find a lowlevel_init.S in your board directory.
198 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
201 *************************************************************************
205 *************************************************************************
211 #define S_FRAME_SIZE 72
233 #define MODE_SVC 0x13
237 * use bad_save_user_regs for abort/prefetch/undef/swi ...
238 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
241 .macro bad_save_user_regs
242 sub sp, sp, #S_FRAME_SIZE
243 stmia sp, {r0 - r12} @ Calling r0-r12
244 ldr r2, IRQ_STACK_START_IN
245 ldmia r2, {r2 - r3} @ get pc, cpsr
246 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
250 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
254 .macro irq_save_user_regs
255 sub sp, sp, #S_FRAME_SIZE
256 stmia sp, {r0 - r12} @ Calling r0-r12
258 stmdb r7, {sp, lr}^ @ Calling SP, LR
259 str lr, [r7, #0] @ Save calling PC
261 str r6, [r7, #4] @ Save CPSR
262 str r0, [r7, #8] @ Save OLD_R0
266 .macro irq_restore_user_regs
267 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
269 ldr lr, [sp, #S_PC] @ Get PC
270 add sp, sp, #S_FRAME_SIZE
271 /* return & move spsr_svc into cpsr */
276 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
278 str lr, [r13] @ save caller lr / spsr
282 mov r13, #MODE_SVC @ prepare SVC-Mode
289 .macro get_irq_stack @ setup IRQ stack
290 ldr sp, IRQ_STACK_START
293 .macro get_fiq_stack @ setup FIQ stack
294 ldr sp, FIQ_STACK_START
301 undefined_instruction:
304 bl do_undefined_instruction
310 bl do_software_interrupt
330 #ifdef CONFIG_USE_IRQ
337 irq_restore_user_regs
342 /* someone ought to write a more effiction fiq_save_user_regs */
345 irq_restore_user_regs