2 * SoC-specific lowlevel code for DA850
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 #include <asm/arch/da850_lowlevel.h>
29 #include <asm/arch/hardware.h>
30 #include <asm/arch/ddr2_defs.h>
31 #include <asm/arch/emif_defs.h>
32 #include <asm/arch/pll_defs.h>
34 void da850_waitloop(unsigned long loopcnt)
38 for (i = 0; i < loopcnt; i++)
42 int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
44 if (reg == davinci_pllc0_regs)
45 /* Unlock PLL registers. */
46 clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
49 * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
52 clrbits_le32(®->pllctl, PLLCTL_PLLENSRC);
53 /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
54 clrbits_le32(®->pllctl, PLLCTL_EXTCLKSRC);
56 /* Set PLLEN=0 => PLL BYPASS MODE */
57 clrbits_le32(®->pllctl, PLLCTL_PLLEN);
61 if (reg == davinci_pllc0_regs) {
63 * Select the Clock Mode bit 8 as External Clock or On Chip
66 dv_maskbits(®->pllctl, ~PLLCTL_RES_9);
67 setbits_le32(®->pllctl,
68 (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
71 /* Clear PLLRST bit to reset the PLL */
72 clrbits_le32(®->pllctl, PLLCTL_PLLRST);
74 /* Disable the PLL output */
75 setbits_le32(®->pllctl, PLLCTL_PLLDIS);
77 /* PLL initialization sequence */
79 * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
82 clrbits_le32(®->pllctl, PLLCTL_PLLPWRDN);
84 /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
85 clrbits_le32(®->pllctl, PLLCTL_PLLDIS);
87 /* Program the required multiplier value in PLLM */
88 writel(pllmult, ®->pllm);
90 /* program the postdiv */
91 if (reg == davinci_pllc0_regs)
92 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
95 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
99 * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
100 * no GO operation is currently in progress
102 while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
105 if (reg == davinci_pllc0_regs) {
106 writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, ®->plldiv1);
107 writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, ®->plldiv2);
108 writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, ®->plldiv3);
109 writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, ®->plldiv4);
110 writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, ®->plldiv5);
111 writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, ®->plldiv6);
112 writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, ®->plldiv7);
114 writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, ®->plldiv1);
115 writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, ®->plldiv2);
116 writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, ®->plldiv3);
120 * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
123 setbits_le32(®->pllcmd, PLLCMD_GOSTAT);
126 * Wait for the GOSTAT bit in PLLSTAT to clear to 0
127 * (completion of phase alignment).
129 while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
132 /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
135 /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
136 setbits_le32(®->pllctl, PLLCTL_PLLRST);
138 /* Wait for PLL to lock. See PLL spec for PLL lock time */
139 da850_waitloop(2400);
142 * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
145 setbits_le32(®->pllctl, PLLCTL_PLLEN);
149 * clear EMIFA and EMIFB clock source settings, let them
152 if (reg == davinci_pllc0_regs)
153 dv_maskbits(&davinci_syscfg_regs->cfgchip3,
154 ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
159 int da850_ddr_setup(void)
163 /* Enable the Clock to DDR2/mDDR */
164 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
166 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
167 if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
168 /* Begin VTP Calibration */
169 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
170 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
171 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
172 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
173 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
175 /* Polling READY bit to see when VTP calibration is done */
176 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
177 while ((tmp & VTP_READY) != VTP_READY)
178 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
180 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
181 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
183 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
186 writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
187 clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
188 (1 << DDR_SLEW_CMOSEN_BIT));
191 * SDRAM Configuration Register (SDCR):
192 * First set the BOOTUNLOCK bit to make configuration bits
195 setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
198 * Write the new value of these bits and clear BOOTUNLOCK.
199 * At the same time, set the TIMUNLOCK bit to allow changing
200 * the timing registers
202 tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
203 tmp &= ~DV_DDR_BOOTUNLOCK;
204 tmp |= DV_DDR_TIMUNLOCK;
205 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
207 /* write memory configuration and timing */
208 writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
209 writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
210 writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
212 /* clear the TIMUNLOCK bit and write the value of the CL field */
213 tmp &= ~DV_DDR_TIMUNLOCK;
214 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
217 * LPMODEN and MCLKSTOPEN must be set!
218 * Without this bits set, PSC don;t switch states !!
220 writel(CONFIG_SYS_DA850_DDR2_SDRCR |
221 (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
222 (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
223 &dv_ddr2_regs_ctrl->sdrcr);
225 /* SyncReset the Clock to EMIF3A SDRAM */
226 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
227 /* Enable the Clock to EMIF3A SDRAM */
228 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
230 /* disable self refresh */
231 clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
232 DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
233 writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
238 void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
241 clrbits_le32(&davinci_syscfg_regs->pinmux[offset], mask);
242 setbits_le32(&davinci_syscfg_regs->pinmux[offset], (mask & value));
245 __attribute__((weak))
246 void board_gpio_init(void)
251 int arch_cpu_init(void)
253 /* Unlock kick registers */
254 writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
255 writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
257 dv_maskbits(&davinci_syscfg_regs->suspsrc,
258 CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
261 da850_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX0);
262 da850_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX1);
263 da850_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX2);
264 da850_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX3);
265 da850_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX4);
266 da850_pinmux_ctl(5, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX5);
267 da850_pinmux_ctl(6, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX6);
268 da850_pinmux_ctl(7, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX7);
269 da850_pinmux_ctl(8, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX8);
270 da850_pinmux_ctl(9, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX9);
271 da850_pinmux_ctl(10, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX10);
272 da850_pinmux_ctl(11, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX11);
273 da850_pinmux_ctl(12, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX12);
274 da850_pinmux_ctl(13, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX13);
275 da850_pinmux_ctl(14, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX14);
276 da850_pinmux_ctl(15, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX15);
277 da850_pinmux_ctl(16, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX16);
278 da850_pinmux_ctl(17, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX17);
279 da850_pinmux_ctl(18, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX18);
280 da850_pinmux_ctl(19, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX19);
283 da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
284 da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
289 /* setup CSn config */
290 #if defined(CONFIG_SYS_DA850_CS2CFG)
291 writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
293 #if defined(CONFIG_SYS_DA850_CS3CFG)
294 writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
297 lpsc_on(CONFIG_SYS_DA850_LPSC_UART);
298 NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
299 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
302 * Fix Power and Emulation Management Register
303 * see sprufw3a.pdf page 37 Table 24
305 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
306 DAVINCI_UART_PWREMU_MGMT_UTRST),
307 &davinci_uart2_ctrl_regs->pwremu_mgmt);