2 * SoC-specific lowlevel code for DA850
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
28 #include <asm/arch/da850_lowlevel.h>
29 #include <asm/arch/hardware.h>
30 #include <asm/arch/davinci_misc.h>
31 #include <asm/arch/ddr2_defs.h>
32 #include <asm/arch/emif_defs.h>
33 #include <asm/arch/pll_defs.h>
35 void da850_waitloop(unsigned long loopcnt)
39 for (i = 0; i < loopcnt; i++)
43 int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
45 if (reg == davinci_pllc0_regs)
46 /* Unlock PLL registers. */
47 clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK);
50 * Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled
53 clrbits_le32(®->pllctl, PLLCTL_PLLENSRC);
54 /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
55 clrbits_le32(®->pllctl, PLLCTL_EXTCLKSRC);
57 /* Set PLLEN=0 => PLL BYPASS MODE */
58 clrbits_le32(®->pllctl, PLLCTL_PLLEN);
62 if (reg == davinci_pllc0_regs) {
64 * Select the Clock Mode bit 8 as External Clock or On Chip
67 dv_maskbits(®->pllctl, ~PLLCTL_RES_9);
68 setbits_le32(®->pllctl,
69 (CONFIG_SYS_DV_CLKMODE << PLLCTL_CLOCK_MODE_SHIFT));
72 /* Clear PLLRST bit to reset the PLL */
73 clrbits_le32(®->pllctl, PLLCTL_PLLRST);
75 /* Disable the PLL output */
76 setbits_le32(®->pllctl, PLLCTL_PLLDIS);
78 /* PLL initialization sequence */
80 * Power up the PLL- PWRDN bit set to 0 to bring the PLL out of
83 clrbits_le32(®->pllctl, PLLCTL_PLLPWRDN);
85 /* Enable the PLL from Disable Mode PLLDIS bit to 0 */
86 clrbits_le32(®->pllctl, PLLCTL_PLLDIS);
88 #if defined(CONFIG_SYS_DA850_PLL0_PREDIV)
89 /* program the prediv */
90 if (reg == davinci_pllc0_regs && CONFIG_SYS_DA850_PLL0_PREDIV)
91 writel((PLL_DIVEN | CONFIG_SYS_DA850_PLL0_PREDIV),
95 /* Program the required multiplier value in PLLM */
96 writel(pllmult, ®->pllm);
98 /* program the postdiv */
99 if (reg == davinci_pllc0_regs)
100 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL0_POSTDIV),
103 writel((PLL_POSTDEN | CONFIG_SYS_DA850_PLL1_POSTDIV),
107 * Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that
108 * no GO operation is currently in progress
110 while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
113 if (reg == davinci_pllc0_regs) {
114 writel(CONFIG_SYS_DA850_PLL0_PLLDIV1, ®->plldiv1);
115 writel(CONFIG_SYS_DA850_PLL0_PLLDIV2, ®->plldiv2);
116 writel(CONFIG_SYS_DA850_PLL0_PLLDIV3, ®->plldiv3);
117 writel(CONFIG_SYS_DA850_PLL0_PLLDIV4, ®->plldiv4);
118 writel(CONFIG_SYS_DA850_PLL0_PLLDIV5, ®->plldiv5);
119 writel(CONFIG_SYS_DA850_PLL0_PLLDIV6, ®->plldiv6);
120 writel(CONFIG_SYS_DA850_PLL0_PLLDIV7, ®->plldiv7);
122 writel(CONFIG_SYS_DA850_PLL1_PLLDIV1, ®->plldiv1);
123 writel(CONFIG_SYS_DA850_PLL1_PLLDIV2, ®->plldiv2);
124 writel(CONFIG_SYS_DA850_PLL1_PLLDIV3, ®->plldiv3);
128 * Set the GOSET bit in PLLCMD to 1 to initiate a new divider
131 setbits_le32(®->pllcmd, PLLCMD_GOSTAT);
134 * Wait for the GOSTAT bit in PLLSTAT to clear to 0
135 * (completion of phase alignment).
137 while ((readl(®->pllstat) & PLLCMD_GOSTAT) == PLLCMD_GOSTAT)
140 /* Wait for PLL to reset properly. See PLL spec for PLL reset time */
143 /* Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset */
144 setbits_le32(®->pllctl, PLLCTL_PLLRST);
146 /* Wait for PLL to lock. See PLL spec for PLL lock time */
147 da850_waitloop(2400);
150 * Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass
153 setbits_le32(®->pllctl, PLLCTL_PLLEN);
157 * clear EMIFA and EMIFB clock source settings, let them
160 if (reg == davinci_pllc0_regs)
161 dv_maskbits(&davinci_syscfg_regs->cfgchip3,
162 ~(PLL_SCSCFG3_DIV45PENA | PLL_SCSCFG3_EMA_CLKSRC));
167 int da850_ddr_setup(void)
171 /* Enable the Clock to DDR2/mDDR */
172 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
174 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
175 if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {
176 /* Begin VTP Calibration */
177 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
178 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
179 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
180 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
181 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ);
183 /* Polling READY bit to see when VTP calibration is done */
184 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
185 while ((tmp & VTP_READY) != VTP_READY)
186 tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
188 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK);
189 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN);
191 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN);
194 writel(CONFIG_SYS_DA850_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
195 clrbits_le32(&davinci_syscfg1_regs->ddr_slew,
196 (1 << DDR_SLEW_CMOSEN_BIT));
199 * SDRAM Configuration Register (SDCR):
200 * First set the BOOTUNLOCK bit to make configuration bits
203 setbits_le32(&dv_ddr2_regs_ctrl->sdbcr, DV_DDR_BOOTUNLOCK);
206 * Write the new value of these bits and clear BOOTUNLOCK.
207 * At the same time, set the TIMUNLOCK bit to allow changing
208 * the timing registers
210 tmp = CONFIG_SYS_DA850_DDR2_SDBCR;
211 tmp &= ~DV_DDR_BOOTUNLOCK;
212 tmp |= DV_DDR_TIMUNLOCK;
213 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
215 /* write memory configuration and timing */
216 writel(CONFIG_SYS_DA850_DDR2_SDBCR2, &dv_ddr2_regs_ctrl->sdbcr2);
217 writel(CONFIG_SYS_DA850_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
218 writel(CONFIG_SYS_DA850_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
220 /* clear the TIMUNLOCK bit and write the value of the CL field */
221 tmp &= ~DV_DDR_TIMUNLOCK;
222 writel(tmp, &dv_ddr2_regs_ctrl->sdbcr);
225 * LPMODEN and MCLKSTOPEN must be set!
226 * Without this bits set, PSC don;t switch states !!
228 writel(CONFIG_SYS_DA850_DDR2_SDRCR |
229 (1 << DV_DDR_SRCR_LPMODEN_SHIFT) |
230 (1 << DV_DDR_SRCR_MCLKSTOPEN_SHIFT),
231 &dv_ddr2_regs_ctrl->sdrcr);
233 /* SyncReset the Clock to EMIF3A SDRAM */
234 lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
235 /* Enable the Clock to EMIF3A SDRAM */
236 lpsc_on(DAVINCI_LPSC_DDR_EMIF);
238 /* disable self refresh */
239 clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr,
240 DV_DDR_SDRCR_LPMODEN | DV_DDR_SDRCR_LPMODEN);
241 writel(CONFIG_SYS_DA850_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
246 __attribute__((weak))
247 void board_gpio_init(void)
252 /* pinmux_resource[] vector is defined in the board specific file */
253 extern const struct pinmux_resource pinmuxes[];
254 extern const int pinmuxes_size;
256 int arch_cpu_init(void)
258 /* Unlock kick registers */
259 writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0);
260 writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1);
262 dv_maskbits(&davinci_syscfg_regs->suspsrc,
263 CONFIG_SYS_DA850_SYSCFG_SUSPSRC);
265 /* configure pinmux settings */
266 if (davinci_configure_pin_mux_items(pinmuxes, pinmuxes_size))
270 da850_pll_init(davinci_pllc0_regs, CONFIG_SYS_DA850_PLL0_PLLM);
271 da850_pll_init(davinci_pllc1_regs, CONFIG_SYS_DA850_PLL1_PLLM);
276 /* setup CSn config */
277 #if defined(CONFIG_SYS_DA850_CS2CFG)
278 writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
280 #if defined(CONFIG_SYS_DA850_CS3CFG)
281 writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
284 lpsc_on(CONFIG_SYS_DA850_LPSC_UART);
285 NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
286 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
289 * Fix Power and Emulation Management Register
290 * see sprufw3a.pdf page 37 Table 24
292 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
293 DAVINCI_UART_PWREMU_MGMT_UTRST),
294 &davinci_uart2_ctrl_regs->pwremu_mgmt);