2 * armboot - Startup Code for ARM926EJS CPU-core
4 * Copyright (c) 2003 Texas Instruments
6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm-offsets.h>
40 *************************************************************************
42 * Jump vector table as in table 3.1 in [1]
44 *************************************************************************
48 #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
53 .word CONFIG_SYS_DV_NOR_BOOT_CFG
60 #ifdef CONFIG_SPL_BUILD
61 /* No exception handlers in preloader */
72 /* pad to 64 byte boundary */
81 ldr pc, _undefined_instruction
82 ldr pc, _software_interrupt
83 ldr pc, _prefetch_abort
89 _undefined_instruction:
90 .word undefined_instruction
92 .word software_interrupt
104 #endif /* CONFIG_SPL_BUILD */
105 .balignl 16,0xdeadbeef
109 *************************************************************************
111 * Startup Code (reset vector)
113 * do important init only if we don't start from memory!
114 * setup Memory and board specific bits prior to relocation.
115 * relocate armboot to ram
118 *************************************************************************
123 #ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
124 .word CONFIG_SYS_TEXT_BASE
126 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
127 .word CONFIG_SPL_TEXT_BASE
129 .word CONFIG_SYS_TEXT_BASE
134 * These are defined in the board-specific linker script.
135 * Subtracting _start from them lets the linker put their
136 * relative position in the executable instead of leaving
139 .globl _bss_start_ofs
141 .word __bss_start - _start
145 .word __bss_end - _start
151 #ifdef CONFIG_NAND_U_BOOT
157 #ifdef CONFIG_USE_IRQ
158 /* IRQ stack memory (calculated at run-time) */
159 .globl IRQ_STACK_START
163 /* IRQ stack memory (calculated at run-time) */
164 .globl FIQ_STACK_START
169 /* IRQ stack memory (calculated at run-time) + 8 bytes */
170 .globl IRQ_STACK_START_IN
175 * the actual reset code
180 * set the cpu to SVC32 mode
188 * we do sys-critical inits only at reboot,
189 * not when booting from ram!
191 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
197 /*------------------------------------------------------------------------------*/
199 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
201 * void relocate_code (addr_sp, gd, addr_moni)
203 * This function relocates the monitor code.
207 mov r4, r0 /* save addr_sp */
208 mov r5, r1 /* save addr of gd */
209 mov r6, r2 /* save addr of destination */
212 sub r9, r6, r0 /* r9 <- relocation offset */
214 moveq r9, #0 /* no relocation. offset(r9) = 0 */
215 beq relocate_done /* skip relocation */
216 mov r1, r6 /* r1 <- scratch for copy loop */
217 ldr r3, _bss_start_ofs
218 add r2, r0, r3 /* r2 <- source end address */
221 ldmia r0!, {r9-r10} /* copy from source address [r0] */
222 stmia r1!, {r9-r10} /* copy to target address [r1] */
223 cmp r0, r2 /* until source end address [r2] */
226 #ifndef CONFIG_SPL_BUILD
228 * fix .rel.dyn relocations
230 ldr r0, _TEXT_BASE /* r0 <- Text base */
231 sub r9, r6, r0 /* r9 <- relocation offset */
232 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
233 add r10, r10, r0 /* r10 <- sym table in FLASH */
234 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
235 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
236 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
237 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
239 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
240 add r0, r0, r9 /* r0 <- location to fix up in RAM */
243 cmp r7, #23 /* relative fixup? */
245 cmp r7, #2 /* absolute fixup? */
247 /* ignore unknown type of fixup */
250 /* absolute fix: set location to (offset) symbol value */
251 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
252 add r1, r10, r1 /* r1 <- address of symbol in table */
253 ldr r1, [r1, #4] /* r1 <- symbol value */
254 add r1, r1, r9 /* r1 <- relocated sym addr */
257 /* relative fix: increase location by offset */
262 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
272 .word __rel_dyn_start - _start
274 .word __rel_dyn_end - _start
276 .word __dynsym_start - _start
280 .globl c_runtime_cpu_setup
286 *************************************************************************
288 * CPU_init_critical registers
290 * setup important registers
291 * setup memory timing
293 *************************************************************************
295 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
298 * flush D cache before disabling it
302 mrc p15, 0, r15, c7, c10, 3
305 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
306 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
309 * disable MMU and D cache
310 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
312 mrc p15, 0, r0, c1, c0, 0
313 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
314 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
315 #ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
316 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
318 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
320 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
321 #ifndef CONFIG_SYS_ICACHE_OFF
322 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
324 mcr p15, 0, r0, c1, c0, 0
327 * Go setup Memory and board specific bits prior to relocation.
329 mov ip, lr /* perserve link reg across call */
330 bl lowlevel_init /* go setup pll,mux,memory */
331 mov lr, ip /* restore link */
332 mov pc, lr /* back to my caller */
333 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
335 #ifndef CONFIG_SPL_BUILD
337 *************************************************************************
341 *************************************************************************
347 #define S_FRAME_SIZE 72
369 #define MODE_SVC 0x13
373 * use bad_save_user_regs for abort/prefetch/undef/swi ...
374 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
377 .macro bad_save_user_regs
378 @ carve out a frame on current user stack
379 sub sp, sp, #S_FRAME_SIZE
380 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
381 ldr r2, IRQ_STACK_START_IN
382 @ get values for "aborted" pc and cpsr (into parm regs)
384 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
387 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
388 mov r0, sp @ save current stack into r0 (param register)
391 .macro irq_save_user_regs
392 sub sp, sp, #S_FRAME_SIZE
393 stmia sp, {r0 - r12} @ Calling r0-r12
394 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
396 stmdb r8, {sp, lr}^ @ Calling SP, LR
397 str lr, [r8, #0] @ Save calling PC
399 str r6, [r8, #4] @ Save CPSR
400 str r0, [r8, #8] @ Save OLD_R0
404 .macro irq_restore_user_regs
405 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
407 ldr lr, [sp, #S_PC] @ Get PC
408 add sp, sp, #S_FRAME_SIZE
409 subs pc, lr, #4 @ return & move spsr_svc into cpsr
413 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
415 str lr, [r13] @ save caller lr in position 0 of saved stack
416 mrs lr, spsr @ get the spsr
417 str lr, [r13, #4] @ save spsr in position 1 of saved stack
418 mov r13, #MODE_SVC @ prepare SVC-Mode
420 msr spsr, r13 @ switch modes, make sure moves will execute
421 mov lr, pc @ capture return pc
422 movs pc, lr @ jump to next instruction & switch modes.
425 .macro get_irq_stack @ setup IRQ stack
426 ldr sp, IRQ_STACK_START
429 .macro get_fiq_stack @ setup FIQ stack
430 ldr sp, FIQ_STACK_START
432 #endif /* CONFIG_SPL_BUILD */
437 #ifdef CONFIG_SPL_BUILD
440 ldr sp, _TEXT_BASE /* switch to abort stack */
442 bl 1b /* hang and never return */
443 #else /* !CONFIG_SPL_BUILD */
445 undefined_instruction:
448 bl do_undefined_instruction
454 bl do_software_interrupt
474 #ifdef CONFIG_USE_IRQ
481 irq_restore_user_regs
486 /* someone ought to write a more effiction fiq_save_user_regs */
489 irq_restore_user_regs
506 #endif /* CONFIG_SPL_BUILD */