2 * armboot - Startup Code for ARM926EJS CPU-core
4 * Copyright (c) 2003 Texas Instruments
6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm-offsets.h>
39 *************************************************************************
41 * Jump vector table as in table 3.1 in [1]
43 *************************************************************************
50 ldr pc, _undefined_instruction
51 ldr pc, _software_interrupt
52 ldr pc, _prefetch_abort
58 _undefined_instruction:
59 .word undefined_instruction
61 .word software_interrupt
73 .balignl 16,0xdeadbeef
78 *************************************************************************
80 * Startup Code (reset vector)
82 * do important init only if we don't start from memory!
83 * setup Memory and board specific bits prior to relocation.
84 * relocate armboot to ram
87 *************************************************************************
92 .word CONFIG_SYS_TEXT_BASE
95 * These are defined in the board-specific linker script.
96 * Subtracting _start from them lets the linker put their
97 * relative position in the executable instead of leaving
100 .globl _bss_start_ofs
102 .word __bss_start - _start
106 .word __bss_end__ - _start
112 #ifdef CONFIG_USE_IRQ
113 /* IRQ stack memory (calculated at run-time) */
114 .globl IRQ_STACK_START
118 /* IRQ stack memory (calculated at run-time) */
119 .globl FIQ_STACK_START
124 /* IRQ stack memory (calculated at run-time) + 8 bytes */
125 .globl IRQ_STACK_START_IN
130 * the actual reset code
135 * set the cpu to SVC32 mode
143 * we do sys-critical inits only at reboot,
144 * not when booting from ram!
146 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
150 /* Set stackpointer in internal RAM to call board_init_f */
152 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
153 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
157 /*------------------------------------------------------------------------------*/
160 * void relocate_code (addr_sp, gd, addr_moni)
162 * This "function" does not return, instead it continues in RAM
163 * after relocating the monitor code.
168 mov r4, r0 /* save addr_sp */
169 mov r5, r1 /* save addr of gd */
170 mov r6, r2 /* save addr of destination */
172 /* Set up the stack */
178 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
179 beq clear_bss /* skip relocation */
180 mov r1, r6 /* r1 <- scratch for copy_loop */
181 ldr r3, _bss_start_ofs
182 add r2, r0, r3 /* r2 <- source end address */
185 ldmia r0!, {r9-r10} /* copy from source address [r0] */
186 stmia r1!, {r9-r10} /* copy to target address [r1] */
187 cmp r0, r2 /* until source end address [r2] */
190 #ifndef CONFIG_SPL_BUILD
192 * fix .rel.dyn relocations
194 ldr r0, _TEXT_BASE /* r0 <- Text base */
195 sub r9, r6, r0 /* r9 <- relocation offset */
196 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
197 add r10, r10, r0 /* r10 <- sym table in FLASH */
198 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
199 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
200 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
201 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
203 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
204 add r0, r0, r9 /* r0 <- location to fix up in RAM */
207 cmp r7, #23 /* relative fixup? */
209 cmp r7, #2 /* absolute fixup? */
211 /* ignore unknown type of fixup */
214 /* absolute fix: set location to (offset) symbol value */
215 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
216 add r1, r10, r1 /* r1 <- address of symbol in table */
217 ldr r1, [r1, #4] /* r1 <- symbol value */
218 add r1, r1, r9 /* r1 <- relocated sym addr */
221 /* relative fix: increase location by offset */
226 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
232 #ifndef CONFIG_SPL_BUILD
233 ldr r0, _bss_start_ofs
235 mov r4, r6 /* reloc addr */
238 mov r2, #0x00000000 /* clear */
240 clbss_l:cmp r0, r1 /* clear loop... */
241 bhs clbss_e /* if reached end of bss, exit */
249 * We are done. Do not return, instead branch to second part of board
250 * initialization, now running from RAM.
252 #ifdef CONFIG_NAND_SPL
255 _nand_boot: .word nand_boot
257 ldr r0, _board_init_r_ofs
261 /* setup parameters for board_init_r */
262 mov r0, r5 /* gd_t */
263 mov r1, r6 /* dest_addr */
268 .word board_init_r - _start
272 .word __rel_dyn_start - _start
274 .word __rel_dyn_end - _start
276 .word __dynsym_start - _start
279 *************************************************************************
281 * CPU_init_critical registers
283 * setup important registers
284 * setup memory timing
286 *************************************************************************
290 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
293 * flush v4 I/D caches
296 mcr p15, 0, r0, c7, c5, 0 /* flush v4 I-cache */
297 mcr p15, 0, r0, c7, c6, 0 /* flush v4 D-cache */
300 * disable MMU stuff and caches
302 mrc p15, 0, r0, c1, c0, 0
303 bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
304 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
305 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
306 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
307 mcr p15, 0, r0, c1, c0, 0
310 * Go setup Memory and board specific bits prior to relocation.
312 mov ip, lr /* perserve link reg across call */
313 bl lowlevel_init /* go setup memory */
314 mov lr, ip /* restore link */
315 mov pc, lr /* back to my caller */
318 *************************************************************************
322 *************************************************************************
328 #define S_FRAME_SIZE 72
350 #define MODE_SVC 0x13
354 * use bad_save_user_regs for abort/prefetch/undef/swi ...
355 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
358 .macro bad_save_user_regs
359 @ carve out a frame on current user stack
360 sub sp, sp, #S_FRAME_SIZE
361 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
363 ldr r2, IRQ_STACK_START_IN
364 @ get values for "aborted" pc and cpsr (into parm regs)
366 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
369 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
370 mov r0, sp @ save current stack into r0 (param register)
373 .macro irq_save_user_regs
374 sub sp, sp, #S_FRAME_SIZE
375 stmia sp, {r0 - r12} @ Calling r0-r12
376 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
378 stmdb r8, {sp, lr}^ @ Calling SP, LR
379 str lr, [r8, #0] @ Save calling PC
381 str r6, [r8, #4] @ Save CPSR
382 str r0, [r8, #8] @ Save OLD_R0
386 .macro irq_restore_user_regs
387 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
389 ldr lr, [sp, #S_PC] @ Get PC
390 add sp, sp, #S_FRAME_SIZE
391 subs pc, lr, #4 @ return & move spsr_svc into cpsr
395 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
397 str lr, [r13] @ save caller lr in position 0 of saved stack
398 mrs lr, spsr @ get the spsr
399 str lr, [r13, #4] @ save spsr in position 1 of saved stack
400 mov r13, #MODE_SVC @ prepare SVC-Mode
402 msr spsr, r13 @ switch modes, make sure moves will execute
403 mov lr, pc @ capture return pc
404 movs pc, lr @ jump to next instruction & switch modes.
407 .macro get_irq_stack @ setup IRQ stack
408 ldr sp, IRQ_STACK_START
411 .macro get_fiq_stack @ setup FIQ stack
412 ldr sp, FIQ_STACK_START
419 undefined_instruction:
422 bl do_undefined_instruction
428 bl do_software_interrupt
448 #ifdef CONFIG_USE_IRQ
455 irq_restore_user_regs
460 /* someone ought to write a more effiction fiq_save_user_regs */
463 irq_restore_user_regs
481 # ifdef CONFIG_INTEGRATOR
483 /* Satisfied by general board level routine */
491 ldr r1, rstctl1 /* get clkm1 reset ctl */
493 strh r3, [r1] /* clear it */
495 strh r3, [r1] /* force dsp+arm reset */
502 #endif /* #ifdef CONFIG_INTEGRATOR */