4 * Common board functions for AM33XX based boards
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mem.h>
21 #include <asm/arch/mmc_host_def.h>
22 #include <asm/arch/sys_proto.h>
29 #include <asm/errno.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/musb.h>
33 #include <asm/omap_musb.h>
35 DECLARE_GLOBAL_DATA_PTR;
37 static const struct gpio_bank gpio_bank_am33xx[4] = {
38 { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
39 { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
40 { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
41 { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
44 const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
46 #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
47 int cpu_mmc_init(bd_t *bis)
51 ret = omap_mmc_init(0, 0, 0, -1, -1);
55 return omap_mmc_init(1, 0, 0, -1, -1);
59 /* AM33XX has two MUSB controllers which can be host or gadget */
60 #if (defined(CONFIG_MUSB_GADGET) || defined(CONFIG_MUSB_HOST)) && \
61 (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1))
62 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
64 /* USB 2.0 PHY Control */
65 #define CM_PHY_PWRDN (1 << 0)
66 #define CM_PHY_OTG_PWRDN (1 << 1)
67 #define OTGVDET_EN (1 << 19)
68 #define OTGSESSENDEN (1 << 20)
70 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
73 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
74 OTGVDET_EN | OTGSESSENDEN);
76 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
80 static struct musb_hdrc_config musb_config = {
87 #ifdef CONFIG_AM335X_USB0
88 static void am33xx_otg0_set_phy_power(u8 on)
90 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
93 struct omap_musb_board_data otg0_board_data = {
94 .set_phy_power = am33xx_otg0_set_phy_power,
97 static struct musb_hdrc_platform_data otg0_plat = {
98 .mode = CONFIG_AM335X_USB0_MODE,
99 .config = &musb_config,
101 .platform_ops = &musb_dsps_ops,
102 .board_data = &otg0_board_data,
106 #ifdef CONFIG_AM335X_USB1
107 static void am33xx_otg1_set_phy_power(u8 on)
109 am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
112 struct omap_musb_board_data otg1_board_data = {
113 .set_phy_power = am33xx_otg1_set_phy_power,
116 static struct musb_hdrc_platform_data otg1_plat = {
117 .mode = CONFIG_AM335X_USB1_MODE,
118 .config = &musb_config,
120 .platform_ops = &musb_dsps_ops,
121 .board_data = &otg1_board_data,
126 int arch_misc_init(void)
128 #ifdef CONFIG_AM335X_USB0
129 musb_register(&otg0_plat, &otg0_board_data,
130 (void *)USB0_OTG_BASE);
132 #ifdef CONFIG_AM335X_USB1
133 musb_register(&otg1_plat, &otg1_board_data,
134 (void *)USB1_OTG_BASE);
139 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
140 static void rtc32k_enable(void)
142 struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
145 * Unlock the RTC's registers. For more details please see the
146 * RTC_SS section of the TRM. In order to unlock we need to
147 * write these specific values (keys) in this order.
149 writel(0x83e70b13, &rtc->kick0r);
150 writel(0x95a4f1e0, &rtc->kick1r);
152 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
153 writel((1 << 3) | (1 << 6), &rtc->osc);
156 static void uart_soft_reset(void)
158 struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
161 regval = readl(&uart_base->uartsyscfg);
162 regval |= UART_RESET;
163 writel(regval, &uart_base->uartsyscfg);
164 while ((readl(&uart_base->uartsyssts) &
165 UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
168 /* Disable smart idle */
169 regval = readl(&uart_base->uartsyscfg);
170 regval |= UART_SMART_IDLE_EN;
171 writel(regval, &uart_base->uartsyscfg);
174 static void watchdog_disable(void)
176 struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
178 writel(0xAAAA, &wdtimer->wdtwspr);
179 while (readl(&wdtimer->wdtwwps) != 0x0)
181 writel(0x5555, &wdtimer->wdtwspr);
182 while (readl(&wdtimer->wdtwwps) != 0x0)
190 * The ROM will only have set up sufficient pinmux to allow for the
191 * first 4KiB NOR to be read, we must finish doing what we know of
192 * the NOR mux in this space in order to continue.
194 #ifdef CONFIG_NOR_BOOT
195 enable_norboot_pin_mux();
198 * Save the boot parameters passed from romcode.
199 * We cannot delay the saving further than this,
200 * to prevent overwrites.
202 #ifdef CONFIG_SPL_BUILD
203 save_omap_boot_params();
205 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
209 setup_clocks_for_console();
212 #ifdef CONFIG_NOR_BOOT
213 gd->baudrate = CONFIG_BAUDRATE;
215 gd->have_console = 1;
218 preloader_console_init();
220 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
223 /* Enable RTC32K clock */