2 * Copyright (c) 2010 Samsung Electronics.
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/system.h>
12 enum l2_cache_params {
13 CACHE_TAG_RAM_SETUP = (1 << 9),
14 CACHE_DATA_RAM_SETUP = (1 << 5),
15 CACHE_TAG_RAM_LATENCY = (2 << 6),
16 CACHE_DATA_RAM_LATENCY = (2 << 0),
17 CACHE_ENABLE_CLEAN_EVICT = (0 << 3),
18 CACHE_DISABLE_CLEAN_EVICT = (1 << 3)
21 void reset_cpu(ulong addr)
23 writel(0x1, samsung_get_base_swreset());
26 #ifndef CONFIG_SYS_DCACHE_OFF
27 void enable_caches(void)
29 /* Enable D-cache. I-cache is already enabled in start.S */
34 #ifndef CONFIG_SYS_L2CACHE_OFF
36 * Set L2 cache parameters
38 static void exynos5_set_l2cache_params(void)
40 unsigned int l2ctlr = 0, l2actlr = 0;
42 /* Read L2CTLR value */
43 asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(l2ctlr));
45 /* Set cache latency cycles */
46 l2ctlr |= CACHE_TAG_RAM_LATENCY |
47 CACHE_DATA_RAM_LATENCY;
49 if (proid_is_exynos5420() || proid_is_exynos5800()) {
50 /* Read L2ACTLR value */
51 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (l2actlr));
53 /* Disable clean/evict push to external */
54 l2actlr |= CACHE_DISABLE_CLEAN_EVICT;
56 /* Write new vlaue to L2ACTLR */
57 asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (l2actlr));
59 /* Set cache setup cycles */
60 l2ctlr |= CACHE_TAG_RAM_SETUP |
64 /* Write new vlaue to L2CTLR */
65 asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(l2ctlr));
69 * Sets L2 cache related parameters before enabling data cache
71 void v7_outer_cache_enable(void)
74 exynos5_set_l2cache_params();