1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015 Freescale Semiconductor, Inc.
4 * Author: Wang Dongsheng <dongsheng.wang@freescale.com>
8 #include <linux/linkage.h>
10 #include <asm/armv7.h>
11 #include <asm/arch-armv7/generictimer.h>
14 #define RCPM_TWAITSR 0x04C
16 #define SCFG_CORE0_SFT_RST 0x130
17 #define SCFG_CORESRENCR 0x204
19 #define DCFG_CCSR_RSTCR 0x0B0
20 #define DCFG_CCSR_RSTCR_RESET_REQ 0x2
21 #define DCFG_CCSR_BRR 0x0E4
22 #define DCFG_CCSR_SCRATCHRW1 0x200
24 #define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0
25 #define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0
26 #define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0
27 #define PSCI_FN_CPU_ON_FEATURE_MASK 0x0
28 #define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0
29 #define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0
30 #define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0
31 #define PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK 0x0
33 .pushsection ._secure.text, "ax"
39 #define ONE_MS (COUNTER_FREQUENCY / 1000)
40 #define RESET_WAIT (30 * ONE_MS)
49 _ls102x_psci_supported_table:
50 .word ARM_PSCI_0_2_FN_PSCI_VERSION
51 .word PSCI_FN_PSCI_VERSION_FEATURE_MASK
52 .word ARM_PSCI_0_2_FN_CPU_SUSPEND
53 .word PSCI_FN_CPU_SUSPEND_FEATURE_MASK
54 .word ARM_PSCI_0_2_FN_CPU_OFF
55 .word PSCI_FN_CPU_OFF_FEATURE_MASK
56 .word ARM_PSCI_0_2_FN_CPU_ON
57 .word PSCI_FN_CPU_ON_FEATURE_MASK
58 .word ARM_PSCI_0_2_FN_AFFINITY_INFO
59 .word PSCI_FN_AFFINITY_INFO_FEATURE_MASK
60 .word ARM_PSCI_0_2_FN_SYSTEM_OFF
61 .word PSCI_FN_SYSTEM_OFF_FEATURE_MASK
62 .word ARM_PSCI_0_2_FN_SYSTEM_RESET
63 .word PSCI_FN_SYSTEM_RESET_FEATURE_MASK
64 .word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND
65 .word PSCI_FN_SYSTEM_SUSPEND_FEATURE_MASK
71 adr r2, _ls102x_psci_supported_table
83 @ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL
84 @ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
85 @ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
86 @ ARM_PSCI_RET_INVAL,suppose caller saves r4 before calling
87 LENTRY(psci_check_target_cpu_id)
88 @ Get the real CPU number
90 mov r0, #ARM_PSCI_RET_INVAL
92 @ Bit[31:24], bits must be zero.
96 @ Affinity level 2 - Cluster: only one cluster in LS1021xa.
100 @ Affinity level 1 - Processors: should be in 0xf00 format.
105 @ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
109 mov r0, #ARM_PSCI_RET_SUCCESS
111 ENDPROC(psci_check_target_cpu_id)
117 push {r4, r5, r6, lr}
119 @ Clear and Get the correct CPU number
121 bl psci_check_target_cpu_id
122 cmp r0, #ARM_PSCI_RET_INVAL
127 bl psci_save_target_pc
130 @ Get DCFG base address
131 movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
132 movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
134 @ Detect target CPU state
135 ldr r2, [r4, #DCFG_CCSR_BRR]
142 @ Get SCFG base address
143 movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
144 movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
146 @ Enable CORE Soft Reset
150 str r5, [r0, #SCFG_CORESRENCR]
152 @ Get CPUx offset register
157 @ Do reset on target CPU
161 str r5, [r2, #SCFG_CORE0_SFT_RST]
164 timer_wait r2, RESET_WAIT
166 @ Disable CORE soft reset
168 str r5, [r0, #SCFG_CORESRENCR]
171 @ Release on target CPU
172 ldr r2, [r4, #DCFG_CCSR_BRR]
174 lsl r6, r6, r1 @ 32 bytes per CPU
178 str r2, [r4, #DCFG_CCSR_BRR]
180 @ Set secondary boot entry
181 ldr r6, =psci_cpu_entry
183 str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
189 mov r0, #ARM_PSCI_RET_SUCCESS
197 bl psci_cpu_off_common
202 .globl psci_affinity_info
206 mov r0, #ARM_PSCI_RET_INVAL
208 @ Verify Affinity level
210 bne out_affinity_info
212 bl psci_check_target_cpu_id
213 cmp r0, #ARM_PSCI_RET_INVAL
214 beq out_affinity_info
217 @ Get RCPM base address
218 movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
219 movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
221 mov r0, #PSCI_AFFINITY_LEVEL_ON
223 @ Detect target CPU state
224 ldr r2, [r4, #RCPM_TWAITSR]
228 beq out_affinity_info
230 mov r0, #PSCI_AFFINITY_LEVEL_OFF
235 .globl psci_system_reset
237 @ Get DCFG base address
238 movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
239 movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
241 mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
243 str r2, [r1, #DCFG_CCSR_RSTCR]
248 .globl psci_system_suspend
252 bl ls1_system_suspend