2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/errno.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/crm_regs.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sys_proto.h>
17 PLL_SYS, /* System PLL */
18 PLL_BUS, /* System Bus PLL*/
19 PLL_USBOTG, /* OTG USB PLL */
20 PLL_ENET, /* ENET PLL */
23 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
25 #ifdef CONFIG_MXC_OCOTP
26 void enable_ocotp_clk(unsigned char enable)
30 reg = __raw_readl(&imx_ccm->CCGR2);
32 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
34 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
35 __raw_writel(reg, &imx_ccm->CCGR2);
39 void enable_usboh3_clk(unsigned char enable)
43 reg = __raw_readl(&imx_ccm->CCGR6);
45 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
47 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
48 __raw_writel(reg, &imx_ccm->CCGR6);
52 #ifdef CONFIG_SYS_I2C_MXC
53 /* i2c_num can be from 0 - 2 */
54 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
62 mask = MXC_CCM_CCGR_CG_MASK
63 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
64 reg = __raw_readl(&imx_ccm->CCGR2);
69 __raw_writel(reg, &imx_ccm->CCGR2);
74 /* spi_num can be from 0 - SPI_MAX_NUM */
75 int enable_spi_clk(unsigned char enable, unsigned spi_num)
80 if (spi_num > SPI_MAX_NUM)
83 mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
84 reg = __raw_readl(&imx_ccm->CCGR1);
89 __raw_writel(reg, &imx_ccm->CCGR1);
92 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
98 div = __raw_readl(&imx_ccm->analog_pll_sys);
99 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
101 return (infreq * div) >> 1;
103 div = __raw_readl(&imx_ccm->analog_pll_528);
104 div &= BM_ANADIG_PLL_528_DIV_SELECT;
106 return infreq * (20 + (div << 1));
108 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
109 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
111 return infreq * (20 + (div << 1));
113 div = __raw_readl(&imx_ccm->analog_pll_enet);
114 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
116 return 25000000 * (div + (div >> 1) + 1);
122 static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
130 /* No PFD3 on PPL2 */
133 div = __raw_readl(&imx_ccm->analog_pfd_528);
134 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
137 div = __raw_readl(&imx_ccm->analog_pfd_480);
138 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK);
141 /* No PFD on other PLL */
145 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >>
146 ANATOP_PFD_FRAC_SHIFT(pfd_num));
149 static u32 get_mcu_main_clk(void)
153 reg = __raw_readl(&imx_ccm->cacrr);
154 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
155 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
156 freq = decode_pll(PLL_SYS, MXC_HCLK);
158 return freq / (reg + 1);
161 u32 get_periph_clk(void)
165 reg = __raw_readl(&imx_ccm->cbcdr);
166 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
167 reg = __raw_readl(&imx_ccm->cbcmr);
168 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
169 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
173 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
183 reg = __raw_readl(&imx_ccm->cbcmr);
184 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
185 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
189 freq = decode_pll(PLL_BUS, MXC_HCLK);
192 freq = mxc_get_pll_pfd(PLL_BUS, 2);
195 freq = mxc_get_pll_pfd(PLL_BUS, 0);
198 /* static / 2 divider */
199 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
209 static u32 get_ipg_clk(void)
213 reg = __raw_readl(&imx_ccm->cbcdr);
214 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
215 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
217 return get_ahb_clk() / (ipg_podf + 1);
220 static u32 get_ipg_per_clk(void)
222 u32 reg, perclk_podf;
224 reg = __raw_readl(&imx_ccm->cscmr1);
225 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
227 return get_ipg_clk() / (perclk_podf + 1);
230 static u32 get_uart_clk(void)
233 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
234 reg = __raw_readl(&imx_ccm->cscdr1);
235 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
236 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
239 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
240 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
242 return freq / (uart_podf + 1);
245 static u32 get_cspi_clk(void)
249 reg = __raw_readl(&imx_ccm->cscdr2);
250 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
251 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
253 return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
256 static u32 get_axi_clk(void)
258 u32 root_freq, axi_podf;
259 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
261 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
262 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
264 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
265 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
266 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
268 root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
270 root_freq = get_periph_clk();
272 return root_freq / (axi_podf + 1);
275 static u32 get_emi_slow_clk(void)
277 u32 emi_clk_sel, emi_slow_podf, cscmr1, root_freq = 0;
279 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
280 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
281 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
282 emi_slow_podf = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
283 emi_slow_podf >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
285 switch (emi_clk_sel) {
287 root_freq = get_axi_clk();
290 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
293 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
296 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
300 return root_freq / (emi_slow_podf + 1);
303 #if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
304 static u32 get_mmdc_ch0_clk(void)
306 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
307 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
310 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
311 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
313 switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
314 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
316 freq = decode_pll(PLL_BUS, MXC_HCLK);
319 freq = mxc_get_pll_pfd(PLL_BUS, 2);
322 freq = mxc_get_pll_pfd(PLL_BUS, 0);
325 /* static / 2 divider */
326 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
329 return freq / (podf + 1);
333 static u32 get_mmdc_ch0_clk(void)
335 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
336 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
337 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
339 return get_periph_clk() / (mmdc_ch0_podf + 1);
343 #ifdef CONFIG_FEC_MXC
344 int enable_fec_anatop_clock(enum enet_freq freq)
347 s32 timeout = 100000;
349 struct anatop_regs __iomem *anatop =
350 (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
352 if (freq < ENET_25MHz || freq > ENET_125MHz)
355 reg = readl(&anatop->pll_enet);
356 reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
359 if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
360 (!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
361 reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN;
362 writel(reg, &anatop->pll_enet);
364 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK)
371 /* Enable FEC clock */
372 reg |= BM_ANADIG_PLL_ENET_ENABLE;
373 reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
374 writel(reg, &anatop->pll_enet);
380 static u32 get_usdhc_clk(u32 port)
382 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
383 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
384 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
388 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
389 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
390 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
394 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
395 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
396 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
400 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
401 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
402 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
406 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
407 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
408 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
416 root_freq = mxc_get_pll_pfd(PLL_BUS, 0);
418 root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
420 return root_freq / (usdhc_podf + 1);
423 u32 imx_get_uartclk(void)
425 return get_uart_clk();
428 u32 imx_get_fecclk(void)
430 return mxc_get_clock(MXC_IPG_CLK);
433 static int enable_enet_pll(uint32_t en)
435 struct mxc_ccm_reg *const imx_ccm
436 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
437 s32 timeout = 100000;
441 reg = readl(&imx_ccm->analog_pll_enet);
442 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
443 writel(reg, &imx_ccm->analog_pll_enet);
444 reg |= BM_ANADIG_PLL_SYS_ENABLE;
446 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
451 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
452 writel(reg, &imx_ccm->analog_pll_enet);
454 writel(reg, &imx_ccm->analog_pll_enet);
459 static void ungate_sata_clock(void)
461 struct mxc_ccm_reg *const imx_ccm =
462 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
464 /* Enable SATA clock. */
465 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
469 static void ungate_pcie_clock(void)
471 struct mxc_ccm_reg *const imx_ccm =
472 (struct mxc_ccm_reg *)CCM_BASE_ADDR;
474 /* Enable PCIe clock. */
475 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
479 int enable_sata_clock(void)
482 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
486 int enable_pcie_clock(void)
488 struct anatop_regs *anatop_regs =
489 (struct anatop_regs *)ANATOP_BASE_ADDR;
490 struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
495 * The register ANATOP_MISC1 is not documented in the Freescale
496 * MX6RM. The register that is mapped in the ANATOP space and
497 * marked as ANATOP_MISC1 is actually documented in the PMU section
498 * of the datasheet as PMU_MISC1.
500 * Switch LVDS clock source to SATA (0xb), disable clock INPUT and
501 * enable clock OUTPUT. This is important for PCI express link that
502 * is clocked from the i.MX6.
504 #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12)
505 #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10)
506 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F
507 clrsetbits_le32(&anatop_regs->ana_misc1,
508 ANADIG_ANA_MISC1_LVDSCLK1_IBEN |
509 ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK,
510 ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb);
512 /* PCIe reference clock sourced from AXI. */
513 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
515 /* Party time! Ungate the clock to the PCIe. */
521 return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
522 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
525 unsigned int mxc_get_clock(enum mxc_clock clk)
529 return get_mcu_main_clk();
531 return get_periph_clk();
533 return get_ahb_clk();
535 return get_ipg_clk();
538 return get_ipg_per_clk();
540 return get_uart_clk();
542 return get_cspi_clk();
544 return get_axi_clk();
545 case MXC_EMI_SLOW_CLK:
546 return get_emi_slow_clk();
548 return get_mmdc_ch0_clk();
550 return get_usdhc_clk(0);
552 return get_usdhc_clk(1);
554 return get_usdhc_clk(2);
556 return get_usdhc_clk(3);
558 return get_ahb_clk();
567 * Dump some core clockes.
569 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
572 freq = decode_pll(PLL_SYS, MXC_HCLK);
573 printf("PLL_SYS %8d MHz\n", freq / 1000000);
574 freq = decode_pll(PLL_BUS, MXC_HCLK);
575 printf("PLL_BUS %8d MHz\n", freq / 1000000);
576 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
577 printf("PLL_OTG %8d MHz\n", freq / 1000000);
578 freq = decode_pll(PLL_ENET, MXC_HCLK);
579 printf("PLL_NET %8d MHz\n", freq / 1000000);
582 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
583 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
584 #ifdef CONFIG_MXC_SPI
585 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
587 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
588 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
589 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
590 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
591 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
592 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
593 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
594 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
595 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
601 void enable_ipu_clock(void)
603 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
605 reg = readl(&mxc_ccm->CCGR3);
606 reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
607 writel(reg, &mxc_ccm->CCGR3);
610 /***************************************************/
613 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,