2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/errno.h>
26 #include <asm/arch/imx-regs.h>
27 #include <asm/arch/crm_regs.h>
28 #include <asm/arch/clock.h>
29 #include <asm/arch/sys_proto.h>
32 PLL_SYS, /* System PLL */
33 PLL_BUS, /* System Bus PLL*/
34 PLL_USBOTG, /* OTG USB PLL */
35 PLL_ENET, /* ENET PLL */
38 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
40 #ifdef CONFIG_MXC_OCOTP
41 void enable_ocotp_clk(unsigned char enable)
45 reg = __raw_readl(&imx_ccm->CCGR2);
47 reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
49 reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK;
50 __raw_writel(reg, &imx_ccm->CCGR2);
54 void enable_usboh3_clk(unsigned char enable)
58 reg = __raw_readl(&imx_ccm->CCGR6);
60 reg |= MXC_CCM_CCGR6_USBOH3_MASK;
62 reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
63 __raw_writel(reg, &imx_ccm->CCGR6);
68 /* i2c_num can be from 0 - 2 */
69 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
77 mask = MXC_CCM_CCGR_CG_MASK
78 << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
79 reg = __raw_readl(&imx_ccm->CCGR2);
84 __raw_writel(reg, &imx_ccm->CCGR2);
89 static u32 decode_pll(enum pll_clocks pll, u32 infreq)
95 div = __raw_readl(&imx_ccm->analog_pll_sys);
96 div &= BM_ANADIG_PLL_SYS_DIV_SELECT;
98 return infreq * (div >> 1);
100 div = __raw_readl(&imx_ccm->analog_pll_528);
101 div &= BM_ANADIG_PLL_528_DIV_SELECT;
103 return infreq * (20 + (div << 1));
105 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);
106 div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT;
108 return infreq * (20 + (div << 1));
110 div = __raw_readl(&imx_ccm->analog_pll_enet);
111 div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
113 return (div == 3 ? 125000000 : 25000000 * (div << 1));
120 static u32 get_mcu_main_clk(void)
124 reg = __raw_readl(&imx_ccm->cacrr);
125 reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
126 reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
127 freq = decode_pll(PLL_SYS, MXC_HCLK);
129 return freq / (reg + 1);
132 u32 get_periph_clk(void)
136 reg = __raw_readl(&imx_ccm->cbcdr);
137 if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
138 reg = __raw_readl(&imx_ccm->cbcmr);
139 reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
140 reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
144 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
154 reg = __raw_readl(&imx_ccm->cbcmr);
155 reg &= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
156 reg >>= MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
160 freq = decode_pll(PLL_BUS, MXC_HCLK);
163 freq = PLL2_PFD2_FREQ;
166 freq = PLL2_PFD0_FREQ;
169 freq = PLL2_PFD2_DIV_FREQ;
179 static u32 get_ipg_clk(void)
183 reg = __raw_readl(&imx_ccm->cbcdr);
184 reg &= MXC_CCM_CBCDR_IPG_PODF_MASK;
185 ipg_podf = reg >> MXC_CCM_CBCDR_IPG_PODF_OFFSET;
187 return get_ahb_clk() / (ipg_podf + 1);
190 static u32 get_ipg_per_clk(void)
192 u32 reg, perclk_podf;
194 reg = __raw_readl(&imx_ccm->cscmr1);
195 perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
197 return get_ipg_clk() / (perclk_podf + 1);
200 static u32 get_uart_clk(void)
204 reg = __raw_readl(&imx_ccm->cscdr1);
206 if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
209 reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
210 uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
212 return freq / (uart_podf + 1);
215 static u32 get_cspi_clk(void)
219 reg = __raw_readl(&imx_ccm->cscdr2);
220 reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
221 cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
223 return PLL3_60M / (cspi_podf + 1);
226 static u32 get_axi_clk(void)
228 u32 root_freq, axi_podf;
229 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
231 axi_podf = cbcdr & MXC_CCM_CBCDR_AXI_PODF_MASK;
232 axi_podf >>= MXC_CCM_CBCDR_AXI_PODF_OFFSET;
234 if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
235 if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
236 root_freq = PLL2_PFD2_FREQ;
238 root_freq = PLL3_PFD1_FREQ;
240 root_freq = get_periph_clk();
242 return root_freq / (axi_podf + 1);
245 static u32 get_emi_slow_clk(void)
247 u32 emi_clk_sel, emi_slow_pof, cscmr1, root_freq = 0;
249 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
250 emi_clk_sel = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
251 emi_clk_sel >>= MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET;
252 emi_slow_pof = cscmr1 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
253 emi_slow_pof >>= MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
255 switch (emi_clk_sel) {
257 root_freq = get_axi_clk();
260 root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
263 root_freq = PLL2_PFD2_FREQ;
266 root_freq = PLL2_PFD0_FREQ;
270 return root_freq / (emi_slow_pof + 1);
274 static u32 get_mmdc_ch0_clk(void)
276 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
277 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
280 podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
281 >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
283 switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
284 MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
286 freq = decode_pll(PLL_BUS, MXC_HCLK);
289 freq = PLL2_PFD2_FREQ;
292 freq = PLL2_PFD0_FREQ;
295 freq = PLL2_PFD2_DIV_FREQ;
298 return freq / (podf + 1);
302 static u32 get_mmdc_ch0_clk(void)
304 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
305 u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
306 MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
308 return get_periph_clk() / (mmdc_ch0_podf + 1);
312 static u32 get_usdhc_clk(u32 port)
314 u32 root_freq = 0, usdhc_podf = 0, clk_sel = 0;
315 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);
316 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);
320 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
321 MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
322 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
326 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
327 MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
328 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
332 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
333 MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
334 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
338 usdhc_podf = (cscdr1 & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
339 MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
340 clk_sel = cscmr1 & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
348 root_freq = PLL2_PFD0_FREQ;
350 root_freq = PLL2_PFD2_FREQ;
352 return root_freq / (usdhc_podf + 1);
355 u32 imx_get_uartclk(void)
357 return get_uart_clk();
360 u32 imx_get_fecclk(void)
362 return decode_pll(PLL_ENET, MXC_HCLK);
365 int enable_sata_clock(void)
368 s32 timeout = 100000;
369 struct mxc_ccm_reg *const imx_ccm
370 = (struct mxc_ccm_reg *) CCM_BASE_ADDR;
372 /* Enable sata clock */
373 reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
374 reg |= MXC_CCM_CCGR5_SATA_MASK;
375 writel(reg, &imx_ccm->CCGR5);
378 reg = readl(&imx_ccm->analog_pll_enet);
379 reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN;
380 writel(reg, &imx_ccm->analog_pll_enet);
381 reg |= BM_ANADIG_PLL_SYS_ENABLE;
383 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)
388 reg &= ~BM_ANADIG_PLL_SYS_BYPASS;
389 writel(reg, &imx_ccm->analog_pll_enet);
390 reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA;
391 writel(reg, &imx_ccm->analog_pll_enet);
396 unsigned int mxc_get_clock(enum mxc_clock clk)
400 return get_mcu_main_clk();
402 return get_periph_clk();
404 return get_ahb_clk();
406 return get_ipg_clk();
409 return get_ipg_per_clk();
411 return get_uart_clk();
413 return get_cspi_clk();
415 return get_axi_clk();
416 case MXC_EMI_SLOW_CLK:
417 return get_emi_slow_clk();
419 return get_mmdc_ch0_clk();
421 return get_usdhc_clk(0);
423 return get_usdhc_clk(1);
425 return get_usdhc_clk(2);
427 return get_usdhc_clk(3);
429 return get_ahb_clk();
438 * Dump some core clockes.
440 int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
443 freq = decode_pll(PLL_SYS, MXC_HCLK);
444 printf("PLL_SYS %8d MHz\n", freq / 1000000);
445 freq = decode_pll(PLL_BUS, MXC_HCLK);
446 printf("PLL_BUS %8d MHz\n", freq / 1000000);
447 freq = decode_pll(PLL_USBOTG, MXC_HCLK);
448 printf("PLL_OTG %8d MHz\n", freq / 1000000);
449 freq = decode_pll(PLL_ENET, MXC_HCLK);
450 printf("PLL_NET %8d MHz\n", freq / 1000000);
453 printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
454 printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000);
455 #ifdef CONFIG_MXC_SPI
456 printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
458 printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000);
459 printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000);
460 printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
461 printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000);
462 printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000);
463 printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000);
464 printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000);
465 printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000);
466 printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
471 void enable_ipu_clock(void)
473 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
475 reg = readl(&mxc_ccm->CCGR3);
476 reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
477 writel(reg, &mxc_ccm->CCGR3);
479 /***************************************************/
482 clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks,