2 * Copyright (C) 2014 Gateworks Corporation
3 * Author: Tim Harvey <tharvey@gateworks.com>
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/types.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/mx6-ddr.h>
12 #include <asm/arch/sys_proto.h>
14 #include <asm/types.h>
16 #if defined(CONFIG_MX6SX)
17 /* Configure MX6SX mmdc iomux */
18 void mx6sx_dram_iocfg(unsigned width,
19 const struct mx6sx_iomux_ddr_regs *ddr,
20 const struct mx6sx_iomux_grp_regs *grp)
22 struct mx6sx_iomux_ddr_regs *mx6_ddr_iomux;
23 struct mx6sx_iomux_grp_regs *mx6_grp_iomux;
25 mx6_ddr_iomux = (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
26 mx6_grp_iomux = (struct mx6sx_iomux_grp_regs *)MX6SX_IOM_GRP_BASE;
29 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
30 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
33 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
36 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
37 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
38 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
41 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
42 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
43 writel(ddr->dram_sdcke0, &mx6_ddr_iomux->dram_sdcke0);
44 writel(ddr->dram_sdcke1, &mx6_ddr_iomux->dram_sdcke1);
45 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
46 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
47 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
50 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
51 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
52 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
54 writel(ddr->dram_sdqs2, &mx6_ddr_iomux->dram_sdqs2);
55 writel(ddr->dram_sdqs3, &mx6_ddr_iomux->dram_sdqs3);
59 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
60 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
61 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
63 writel(grp->grp_b2ds, &mx6_grp_iomux->grp_b2ds);
64 writel(grp->grp_b3ds, &mx6_grp_iomux->grp_b3ds);
66 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
67 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
69 writel(ddr->dram_dqm2, &mx6_ddr_iomux->dram_dqm2);
70 writel(ddr->dram_dqm3, &mx6_ddr_iomux->dram_dqm3);
76 void mx6ul_dram_iocfg(unsigned width,
77 const struct mx6ul_iomux_ddr_regs *ddr,
78 const struct mx6ul_iomux_grp_regs *grp)
80 struct mx6ul_iomux_ddr_regs *mx6_ddr_iomux;
81 struct mx6ul_iomux_grp_regs *mx6_grp_iomux;
83 mx6_ddr_iomux = (struct mx6ul_iomux_ddr_regs *)MX6UL_IOM_DDR_BASE;
84 mx6_grp_iomux = (struct mx6ul_iomux_grp_regs *)MX6UL_IOM_GRP_BASE;
87 writel(grp->grp_ddr_type, &mx6_grp_iomux->grp_ddr_type);
88 writel(grp->grp_ddrpke, &mx6_grp_iomux->grp_ddrpke);
91 writel(ddr->dram_sdclk_0, &mx6_ddr_iomux->dram_sdclk_0);
94 writel(ddr->dram_cas, &mx6_ddr_iomux->dram_cas);
95 writel(ddr->dram_ras, &mx6_ddr_iomux->dram_ras);
96 writel(grp->grp_addds, &mx6_grp_iomux->grp_addds);
99 writel(ddr->dram_reset, &mx6_ddr_iomux->dram_reset);
100 writel(ddr->dram_sdba2, &mx6_ddr_iomux->dram_sdba2);
101 writel(ddr->dram_odt0, &mx6_ddr_iomux->dram_odt0);
102 writel(ddr->dram_odt1, &mx6_ddr_iomux->dram_odt1);
103 writel(grp->grp_ctlds, &mx6_grp_iomux->grp_ctlds);
106 writel(grp->grp_ddrmode_ctl, &mx6_grp_iomux->grp_ddrmode_ctl);
107 writel(ddr->dram_sdqs0, &mx6_ddr_iomux->dram_sdqs0);
108 writel(ddr->dram_sdqs1, &mx6_ddr_iomux->dram_sdqs1);
111 writel(grp->grp_ddrmode, &mx6_grp_iomux->grp_ddrmode);
112 writel(grp->grp_b0ds, &mx6_grp_iomux->grp_b0ds);
113 writel(grp->grp_b1ds, &mx6_grp_iomux->grp_b1ds);
114 writel(ddr->dram_dqm0, &mx6_ddr_iomux->dram_dqm0);
115 writel(ddr->dram_dqm1, &mx6_ddr_iomux->dram_dqm1);
119 #if defined(CONFIG_MX6SL)
120 void mx6sl_dram_iocfg(unsigned width,
121 const struct mx6sl_iomux_ddr_regs *ddr,
122 const struct mx6sl_iomux_grp_regs *grp)
124 struct mx6sl_iomux_ddr_regs *mx6_ddr_iomux;
125 struct mx6sl_iomux_grp_regs *mx6_grp_iomux;
127 mx6_ddr_iomux = (struct mx6sl_iomux_ddr_regs *)MX6SL_IOM_DDR_BASE;
128 mx6_grp_iomux = (struct mx6sl_iomux_grp_regs *)MX6SL_IOM_GRP_BASE;
131 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
132 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
135 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
138 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
139 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
140 mx6_grp_iomux->grp_addds = grp->grp_addds;
143 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
144 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
145 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
148 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
149 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
150 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
152 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
153 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
157 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
158 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
159 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
161 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
162 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
165 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
166 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
168 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
169 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
174 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
175 /* Configure MX6DQ mmdc iomux */
176 void mx6dq_dram_iocfg(unsigned width,
177 const struct mx6dq_iomux_ddr_regs *ddr,
178 const struct mx6dq_iomux_grp_regs *grp)
180 volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
181 volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
183 mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
184 mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
187 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
188 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
191 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
192 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
195 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
196 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
197 mx6_grp_iomux->grp_addds = grp->grp_addds;
200 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
201 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
202 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
203 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
204 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
205 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
206 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
209 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
210 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
211 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
213 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
214 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
217 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
218 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
219 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
220 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
224 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
225 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
226 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
228 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
229 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
232 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
233 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
234 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
235 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
237 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
238 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
240 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
241 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
244 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
245 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
246 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
247 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
252 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
253 /* Configure MX6SDL mmdc iomux */
254 void mx6sdl_dram_iocfg(unsigned width,
255 const struct mx6sdl_iomux_ddr_regs *ddr,
256 const struct mx6sdl_iomux_grp_regs *grp)
258 volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
259 volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
261 mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
262 mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
265 mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
266 mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
269 mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
270 mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
273 mx6_ddr_iomux->dram_cas = ddr->dram_cas;
274 mx6_ddr_iomux->dram_ras = ddr->dram_ras;
275 mx6_grp_iomux->grp_addds = grp->grp_addds;
278 mx6_ddr_iomux->dram_reset = ddr->dram_reset;
279 mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
280 mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
281 mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
282 mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
283 mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
284 mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
287 mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
288 mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
289 mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
291 mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
292 mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
295 mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
296 mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
297 mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
298 mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
302 mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
303 mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
304 mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
306 mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
307 mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
310 mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
311 mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
312 mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
313 mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
315 mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
316 mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
318 mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
319 mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
322 mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
323 mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
324 mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
325 mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
331 * Configure mx6 mmdc registers based on:
332 * - board-specific memory configuration
333 * - board-specific calibration data
334 * - ddr3/lpddr2 chip details
336 * The various calculations here are derived from the Freescale
337 * 1. i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate
338 * MMDC configuration registers based on memory system and memory chip
341 * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
342 * configuration registers based on memory system and memory chip
345 * The defaults here are those which were specified in the spreadsheet.
346 * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
347 * and/or IMX6SLRM section titled MMDC initialization.
349 #define MR(val, ba, cmd, cs1) \
350 ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
351 #define MMDC1(entry, value) do { \
352 if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \
353 !is_cpu_type(MXC_CPU_MX6SL)) \
354 mmdc1->entry = value; \
358 * According JESD209-2B-LPDDR2: Table 103
361 static int lpddr2_wl(uint32_t mem_speed)
376 puts("invalid memory speed\n");
384 * According JESD209-2B-LPDDR2: Table 103
387 static int lpddr2_rl(uint32_t mem_speed)
404 puts("invalid memory speed\n");
411 void mx6_lpddr2_cfg(const struct mx6_ddr_sysinfo *sysinfo,
412 const struct mx6_mmdc_calibration *calib,
413 const struct mx6_lpddr2_cfg *lpddr2_cfg)
415 volatile struct mmdc_p_regs *mmdc0;
417 u8 tcke, tcksrx, tcksre, trrd;
418 u8 twl, txp, tfaw, tcl;
419 u16 tras, twr, tmrd, trtp, twtr, trfc, txsr;
420 u16 trcd_lp, trppb_lp, trpab_lp, trc_lp;
423 int clkper; /* clock period in picoseconds */
424 int clock; /* clock freq in mHz */
427 /* only support 16/32 bits */
428 if (sysinfo->dsize > 1)
431 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
433 clock = mxc_get_clock(MXC_DDR_CLK) / 1000000U;
434 clkper = (1000 * 1000) / clock; /* pico seconds */
436 twl = lpddr2_wl(lpddr2_cfg->mem_speed) - 1;
438 /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */
439 switch (lpddr2_cfg->density) {
443 trfc = DIV_ROUND_UP(130000, clkper) - 1;
444 txsr = DIV_ROUND_UP(140000, clkper) - 1;
447 trfc = DIV_ROUND_UP(210000, clkper) - 1;
448 txsr = DIV_ROUND_UP(220000, clkper) - 1;
452 * 64Mb, 128Mb, 256Mb, 512Mb are not supported currently.
458 * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode,
460 txp = DIV_ROUND_UP(7500, clkper) - 1;
462 if (lpddr2_cfg->mem_speed == 333)
463 tfaw = DIV_ROUND_UP(60000, clkper) - 1;
465 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
466 trrd = DIV_ROUND_UP(10000, clkper) - 1;
468 /* tckesr for LPDDR2 */
469 tcksre = DIV_ROUND_UP(15000, clkper);
471 twr = DIV_ROUND_UP(15000, clkper) - 1;
474 * tMRD should be set to max(tMRR, tMRW)
477 tras = DIV_ROUND_UP(lpddr2_cfg->trasmin, clkper / 10) - 1;
478 /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */
479 trcd_lp = DIV_ROUND_UP(lpddr2_cfg->trcd_lp, clkper / 10) - 1;
480 trc_lp = DIV_ROUND_UP(lpddr2_cfg->trasmin + lpddr2_cfg->trppb_lp,
482 trppb_lp = DIV_ROUND_UP(lpddr2_cfg->trppb_lp, clkper / 10) - 1;
483 trpab_lp = DIV_ROUND_UP(lpddr2_cfg->trpab_lp, clkper / 10) - 1;
484 /* To LPDDR2, CL in MDCFG0 refers to RL */
485 tcl = lpddr2_rl(lpddr2_cfg->mem_speed) - 3;
486 twtr = DIV_ROUND_UP(7500, clkper) - 1;
487 trtp = DIV_ROUND_UP(7500, clkper) - 1;
489 cs0_end = 4 * sysinfo->cs_density - 1;
491 debug("density:%d Gb (%d Gb per chip)\n",
492 sysinfo->cs_density, lpddr2_cfg->density);
493 debug("clock: %dMHz (%d ps)\n", clock, clkper);
494 debug("memspd:%d\n", lpddr2_cfg->mem_speed);
495 debug("trcd_lp=%d\n", trcd_lp);
496 debug("trppb_lp=%d\n", trppb_lp);
497 debug("trpab_lp=%d\n", trpab_lp);
498 debug("trc_lp=%d\n", trc_lp);
499 debug("tcke=%d\n", tcke);
500 debug("tcksrx=%d\n", tcksrx);
501 debug("tcksre=%d\n", tcksre);
502 debug("trfc=%d\n", trfc);
503 debug("txsr=%d\n", txsr);
504 debug("txp=%d\n", txp);
505 debug("tfaw=%d\n", tfaw);
506 debug("tcl=%d\n", tcl);
507 debug("tras=%d\n", tras);
508 debug("twr=%d\n", twr);
509 debug("tmrd=%d\n", tmrd);
510 debug("twl=%d\n", twl);
511 debug("trtp=%d\n", trtp);
512 debug("twtr=%d\n", twtr);
513 debug("trrd=%d\n", trrd);
514 debug("cs0_end=%d\n", cs0_end);
515 debug("ncs=%d\n", sysinfo->ncs);
518 * board-specific configuration:
519 * These values are determined empirically and vary per board layout
521 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
522 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
523 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
524 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
525 mmdc0->mprddlctl = calib->p0_mprddlctl;
526 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
527 mmdc0->mpzqlp2ctl = calib->mpzqlp2ctl;
529 /* Read data DQ Byte0-3 delay */
530 mmdc0->mprddqby0dl = 0x33333333;
531 mmdc0->mprddqby1dl = 0x33333333;
532 if (sysinfo->dsize > 0) {
533 mmdc0->mprddqby2dl = 0x33333333;
534 mmdc0->mprddqby3dl = 0x33333333;
537 /* Write data DQ Byte0-3 delay */
538 mmdc0->mpwrdqby0dl = 0xf3333333;
539 mmdc0->mpwrdqby1dl = 0xf3333333;
540 if (sysinfo->dsize > 0) {
541 mmdc0->mpwrdqby2dl = 0xf3333333;
542 mmdc0->mpwrdqby3dl = 0xf3333333;
546 * In LPDDR2 mode this register should be cleared,
547 * so no termination will be activated.
549 mmdc0->mpodtctrl = 0;
551 /* complete calibration */
552 val = (1 << 11); /* Force measurement on delay-lines */
555 /* Step 1: configuration request */
556 mmdc0->mdscr = (u32)(1 << 15); /* config request */
558 /* Step 2: Timing configuration */
559 mmdc0->mdcfg0 = (trfc << 24) | (txsr << 16) | (txp << 13) |
561 mmdc0->mdcfg1 = (tras << 16) | (twr << 9) | (tmrd << 5) | twl;
562 mmdc0->mdcfg2 = (trtp << 6) | (twtr << 3) | trrd;
563 mmdc0->mdcfg3lp = (trc_lp << 16) | (trcd_lp << 8) |
564 (trppb_lp << 4) | trpab_lp;
567 mmdc0->mdasp = cs0_end; /* CS addressing */
569 /* Step 3: Configure DDR type */
570 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
571 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
572 (sysinfo->ralat << 6) | (1 << 3);
574 /* Step 4: Configure delay while leaving reset */
575 mmdc0->mdor = (sysinfo->sde_to_rst << 8) |
576 (sysinfo->rst_to_cke << 0);
578 /* Step 5: Configure DDR physical parameters (density and burst len) */
579 coladdr = lpddr2_cfg->coladdr;
580 if (lpddr2_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
582 else if (lpddr2_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
584 mmdc0->mdctl = (lpddr2_cfg->rowaddr - 11) << 24 | /* ROW */
585 (coladdr - 9) << 20 | /* COL */
586 (0 << 19) | /* Burst Length = 4 for LPDDR2 */
587 (sysinfo->dsize << 16); /* DDR data bus size */
589 /* Step 6: Perform ZQ calibration */
590 val = 0xa1390003; /* one-time HW ZQ calib */
591 mmdc0->mpzqhwctrl = val;
593 /* Step 7: Enable MMDC with desired chip select */
594 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
595 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
597 /* Step 8: Write Mode Registers to Init LPDDR2 devices */
598 for (cs = 0; cs < sysinfo->ncs; cs++) {
600 mmdc0->mdscr = MR(63, 0, 3, cs);
601 /* MR10: calibration,
602 * 0xff is calibration command after intilization.
604 val = 0xA | (0xff << 8);
605 mmdc0->mdscr = MR(val, 0, 3, cs);
607 val = 0x1 | (0x82 << 8);
608 mmdc0->mdscr = MR(val, 0, 3, cs);
610 val = 0x2 | (0x04 << 8);
611 mmdc0->mdscr = MR(val, 0, 3, cs);
613 val = 0x3 | (0x02 << 8);
614 mmdc0->mdscr = MR(val, 0, 3, cs);
617 /* Step 10: Power down control and self-refresh */
618 mmdc0->mdpdc = (tcke & 0x7) << 16 |
619 5 << 12 | /* PWDT_1: 256 cycles */
620 5 << 8 | /* PWDT_0: 256 cycles */
621 1 << 6 | /* BOTH_CS_PD */
622 (tcksrx & 0x7) << 3 |
624 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
626 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
628 mmdc0->mpzqhwctrl = val;
630 /* Step 12: Configure and activate periodic refresh */
631 mmdc0->mdref = (0 << 14) | /* REF_SEL: Periodic refresh cycle: 64kHz */
632 (3 << 11); /* REFR: Refresh Rate - 4 refreshes */
634 /* Step 13: Deassert config request - init complete */
635 mmdc0->mdscr = 0x00000000;
637 /* wait for auto-ZQ calibration to complete */
641 void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
642 const struct mx6_mmdc_calibration *calib,
643 const struct mx6_ddr3_cfg *ddr3_cfg)
645 volatile struct mmdc_p_regs *mmdc0;
646 volatile struct mmdc_p_regs *mmdc1;
648 u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
649 u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
650 u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
651 u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
653 u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
655 int clkper; /* clock period in picoseconds */
656 int clock; /* clock freq in MHz */
658 u16 mem_speed = ddr3_cfg->mem_speed;
660 mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
661 if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) &&
662 !is_cpu_type(MXC_CPU_MX6SL))
663 mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
665 /* Limit mem_speed for MX6D/MX6Q */
666 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
667 if (mem_speed > 1066)
668 mem_speed = 1066; /* 1066 MT/s */
672 /* Limit mem_speed for MX6S/MX6DL */
675 mem_speed = 800; /* 800 MT/s */
680 clock = mem_speed / 2;
682 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
683 * up to 528 MHz, so reduce the clock to fit chip specs
685 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
687 clock = 528; /* 528 MHz */
690 clkper = (1000 * 1000) / clock; /* pico seconds */
695 switch (ddr3_cfg->density) {
696 case 1: /* 1Gb per chip */
697 trfc = DIV_ROUND_UP(110000, clkper) - 1;
698 txs = DIV_ROUND_UP(120000, clkper) - 1;
700 case 2: /* 2Gb per chip */
701 trfc = DIV_ROUND_UP(160000, clkper) - 1;
702 txs = DIV_ROUND_UP(170000, clkper) - 1;
704 case 4: /* 4Gb per chip */
705 trfc = DIV_ROUND_UP(260000, clkper) - 1;
706 txs = DIV_ROUND_UP(270000, clkper) - 1;
708 case 8: /* 8Gb per chip */
709 trfc = DIV_ROUND_UP(350000, clkper) - 1;
710 txs = DIV_ROUND_UP(360000, clkper) - 1;
713 /* invalid density */
714 puts("invalid chip density\n");
722 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
723 tcke = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
724 if (ddr3_cfg->pagesz == 1) {
725 tfaw = DIV_ROUND_UP(40000, clkper) - 1;
726 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
728 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
729 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
733 txp = DIV_ROUND_UP(max(3 * clkper, 7500), clkper) - 1;
734 tcke = DIV_ROUND_UP(max(3 * clkper, 5625), clkper) - 1;
735 if (ddr3_cfg->pagesz == 1) {
736 tfaw = DIV_ROUND_UP(37500, clkper) - 1;
737 trrd = DIV_ROUND_UP(max(4 * clkper, 7500), clkper) - 1;
739 tfaw = DIV_ROUND_UP(50000, clkper) - 1;
740 trrd = DIV_ROUND_UP(max(4 * clkper, 10000), clkper) - 1;
744 puts("invalid memory speed\n");
748 txpdll = DIV_ROUND_UP(max(10 * clkper, 24000), clkper) - 1;
749 tcksre = DIV_ROUND_UP(max(5 * clkper, 10000), clkper);
750 taonpd = DIV_ROUND_UP(2000, clkper) - 1;
753 twr = DIV_ROUND_UP(15000, clkper) - 1;
754 tmrd = DIV_ROUND_UP(max(12 * clkper, 15000), clkper) - 1;
755 trc = DIV_ROUND_UP(ddr3_cfg->trcmin, clkper / 10) - 1;
756 tras = DIV_ROUND_UP(ddr3_cfg->trasmin, clkper / 10) - 1;
757 tcl = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 3;
758 trp = DIV_ROUND_UP(ddr3_cfg->trcd, clkper / 10) - 1;
759 twtr = ROUND(max(4 * clkper, 7500) / clkper, 1) - 1;
762 cs0_end = 4 * sysinfo->cs_density - 1;
764 debug("density:%d Gb (%d Gb per chip)\n",
765 sysinfo->cs_density, ddr3_cfg->density);
766 debug("clock: %dMHz (%d ps)\n", clock, clkper);
767 debug("memspd:%d\n", mem_speed);
768 debug("tcke=%d\n", tcke);
769 debug("tcksrx=%d\n", tcksrx);
770 debug("tcksre=%d\n", tcksre);
771 debug("taofpd=%d\n", taofpd);
772 debug("taonpd=%d\n", taonpd);
773 debug("todtlon=%d\n", todtlon);
774 debug("tanpd=%d\n", tanpd);
775 debug("taxpd=%d\n", taxpd);
776 debug("trfc=%d\n", trfc);
777 debug("txs=%d\n", txs);
778 debug("txp=%d\n", txp);
779 debug("txpdll=%d\n", txpdll);
780 debug("tfaw=%d\n", tfaw);
781 debug("tcl=%d\n", tcl);
782 debug("trcd=%d\n", trcd);
783 debug("trp=%d\n", trp);
784 debug("trc=%d\n", trc);
785 debug("tras=%d\n", tras);
786 debug("twr=%d\n", twr);
787 debug("tmrd=%d\n", tmrd);
788 debug("tcwl=%d\n", tcwl);
789 debug("tdllk=%d\n", tdllk);
790 debug("trtp=%d\n", trtp);
791 debug("twtr=%d\n", twtr);
792 debug("trrd=%d\n", trrd);
793 debug("txpr=%d\n", txpr);
794 debug("cs0_end=%d\n", cs0_end);
795 debug("ncs=%d\n", sysinfo->ncs);
796 debug("Rtt_wr=%d\n", sysinfo->rtt_wr);
797 debug("Rtt_nom=%d\n", sysinfo->rtt_nom);
798 debug("SRT=%d\n", ddr3_cfg->SRT);
799 debug("tcl=%d\n", tcl);
800 debug("twr=%d\n", twr);
803 * board-specific configuration:
804 * These values are determined empirically and vary per board layout
806 * appnote, ddr3 spreadsheet
808 mmdc0->mpwldectrl0 = calib->p0_mpwldectrl0;
809 mmdc0->mpwldectrl1 = calib->p0_mpwldectrl1;
810 mmdc0->mpdgctrl0 = calib->p0_mpdgctrl0;
811 mmdc0->mpdgctrl1 = calib->p0_mpdgctrl1;
812 mmdc0->mprddlctl = calib->p0_mprddlctl;
813 mmdc0->mpwrdlctl = calib->p0_mpwrdlctl;
814 if (sysinfo->dsize > 1) {
815 MMDC1(mpwldectrl0, calib->p1_mpwldectrl0);
816 MMDC1(mpwldectrl1, calib->p1_mpwldectrl1);
817 MMDC1(mpdgctrl0, calib->p1_mpdgctrl0);
818 MMDC1(mpdgctrl1, calib->p1_mpdgctrl1);
819 MMDC1(mprddlctl, calib->p1_mprddlctl);
820 MMDC1(mpwrdlctl, calib->p1_mpwrdlctl);
823 /* Read data DQ Byte0-3 delay */
824 mmdc0->mprddqby0dl = 0x33333333;
825 mmdc0->mprddqby1dl = 0x33333333;
826 if (sysinfo->dsize > 0) {
827 mmdc0->mprddqby2dl = 0x33333333;
828 mmdc0->mprddqby3dl = 0x33333333;
831 if (sysinfo->dsize > 1) {
832 MMDC1(mprddqby0dl, 0x33333333);
833 MMDC1(mprddqby1dl, 0x33333333);
834 MMDC1(mprddqby2dl, 0x33333333);
835 MMDC1(mprddqby3dl, 0x33333333);
838 /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
839 val = (sysinfo->rtt_nom == 2) ? 0x00011117 : 0x00022227;
840 mmdc0->mpodtctrl = val;
841 if (sysinfo->dsize > 1)
842 MMDC1(mpodtctrl, val);
844 /* complete calibration */
845 val = (1 << 11); /* Force measurement on delay-lines */
847 if (sysinfo->dsize > 1)
850 /* Step 1: configuration request */
851 mmdc0->mdscr = (u32)(1 << 15); /* config request */
853 /* Step 2: Timing configuration */
854 mmdc0->mdcfg0 = (trfc << 24) | (txs << 16) | (txp << 13) |
855 (txpdll << 9) | (tfaw << 4) | tcl;
856 mmdc0->mdcfg1 = (trcd << 29) | (trp << 26) | (trc << 21) |
857 (tras << 16) | (1 << 15) /* trpa */ |
858 (twr << 9) | (tmrd << 5) | tcwl;
859 mmdc0->mdcfg2 = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
860 mmdc0->mdotc = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) |
861 (taxpd << 16) | (todtlon << 12) | (todt_idle_off << 4);
862 mmdc0->mdasp = cs0_end; /* CS addressing */
864 /* Step 3: Configure DDR type */
865 mmdc0->mdmisc = (sysinfo->cs1_mirror << 19) | (sysinfo->walat << 16) |
866 (sysinfo->bi_on << 12) | (sysinfo->mif3_mode << 9) |
867 (sysinfo->ralat << 6);
869 /* Step 4: Configure delay while leaving reset */
870 mmdc0->mdor = (txpr << 16) | (sysinfo->sde_to_rst << 8) |
871 (sysinfo->rst_to_cke << 0);
873 /* Step 5: Configure DDR physical parameters (density and burst len) */
874 coladdr = ddr3_cfg->coladdr;
875 if (ddr3_cfg->coladdr == 8) /* 8-bit COL is 0x3 */
877 else if (ddr3_cfg->coladdr == 12) /* 12-bit COL is 0x4 */
879 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */
880 (coladdr - 9) << 20 | /* COL */
881 (1 << 19) | /* Burst Length = 8 for DDR3 */
882 (sysinfo->dsize << 16); /* DDR data bus size */
884 /* Step 6: Perform ZQ calibration */
885 val = 0xa1390001; /* one-time HW ZQ calib */
886 mmdc0->mpzqhwctrl = val;
887 if (sysinfo->dsize > 1)
888 MMDC1(mpzqhwctrl, val);
890 /* Step 7: Enable MMDC with desired chip select */
891 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */
892 ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
894 /* Step 8: Write Mode Registers to Init DDR3 devices */
895 for (cs = 0; cs < sysinfo->ncs; cs++) {
897 val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |
898 ((tcwl - 3) & 3) << 3;
899 debug("MR2 CS%d: 0x%08x\n", cs, (u32)MR(val, 2, 3, cs));
900 mmdc0->mdscr = MR(val, 2, 3, cs);
902 debug("MR3 CS%d: 0x%08x\n", cs, (u32)MR(0, 3, 3, cs));
903 mmdc0->mdscr = MR(0, 3, 3, cs);
905 val = ((sysinfo->rtt_nom & 1) ? 1 : 0) << 2 |
906 ((sysinfo->rtt_nom & 2) ? 1 : 0) << 6;
907 debug("MR1 CS%d: 0x%08x\n", cs, (u32)MR(val, 1, 3, cs));
908 mmdc0->mdscr = MR(val, 1, 3, cs);
910 val = ((tcl - 1) << 4) | /* CAS */
911 (1 << 8) | /* DLL Reset */
912 ((twr - 3) << 9) | /* Write Recovery */
913 (sysinfo->pd_fast_exit << 12); /* Precharge PD PLL on */
914 debug("MR0 CS%d: 0x%08x\n", cs, (u32)MR(val, 0, 3, cs));
915 mmdc0->mdscr = MR(val, 0, 3, cs);
918 mmdc0->mdscr = MR(val, 0, 4, cs);
921 /* Step 10: Power down control and self-refresh */
922 mmdc0->mdpdc = (tcke & 0x7) << 16 |
923 5 << 12 | /* PWDT_1: 256 cycles */
924 5 << 8 | /* PWDT_0: 256 cycles */
925 1 << 6 | /* BOTH_CS_PD */
926 (tcksrx & 0x7) << 3 |
928 if (!sysinfo->pd_fast_exit)
929 mmdc0->mdpdc |= (1 << 7); /* SLOW_PD */
930 mmdc0->mapsr = 0x00001006; /* ADOPT power down enabled */
932 /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
934 mmdc0->mpzqhwctrl = val;
935 if (sysinfo->dsize > 1)
936 MMDC1(mpzqhwctrl, val);
938 /* Step 12: Configure and activate periodic refresh */
939 mmdc0->mdref = (1 << 14) | /* REF_SEL: Periodic refresh cycle: 32kHz */
940 (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
942 /* Step 13: Deassert config request - init complete */
943 mmdc0->mdscr = 0x00000000;
945 /* wait for auto-ZQ calibration to complete */
949 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
950 const struct mx6_mmdc_calibration *calib,
953 if (sysinfo->ddr_type == DDR_TYPE_DDR3) {
954 mx6_ddr3_cfg(sysinfo, calib, ddr_cfg);
955 } else if (sysinfo->ddr_type == DDR_TYPE_LPDDR2) {
956 mx6_lpddr2_cfg(sysinfo, calib, ddr_cfg);
958 puts("Unsupported ddr type\n");