3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/armv7.h>
12 #include <asm/bootm.h>
13 #include <asm/pl310.h>
14 #include <asm/errno.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/clock.h>
18 #include <asm/arch/sys_proto.h>
19 #include <asm/imx-common/boot_mode.h>
20 #include <asm/imx-common/dma.h>
22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/arch/crm_regs.h>
25 #include <imx_thermal.h>
41 #if defined(CONFIG_IMX6_THERMAL)
42 static const struct imx_thermal_plat imx6_thermal_plat = {
43 .regs = (void *)ANATOP_BASE_ADDR,
48 U_BOOT_DEVICE(imx6_thermal) = {
49 .name = "imx_thermal",
50 .platdata = &imx6_thermal_plat,
56 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
57 return readl(&scu->config) & 3;
62 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
63 u32 reg = readl(&anatop->digprog_sololite);
64 u32 type = ((reg >> 16) & 0xff);
67 if (type != MXC_CPU_MX6SL) {
68 reg = readl(&anatop->digprog);
69 struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
70 cfg = readl(&scu->config) & 3;
71 type = ((reg >> 16) & 0xff);
72 if (type == MXC_CPU_MX6DL) {
74 type = MXC_CPU_MX6SOLO;
77 if (type == MXC_CPU_MX6Q) {
83 major = ((reg >> 8) & 0xff);
85 ((type == MXC_CPU_MX6Q) || (type == MXC_CPU_MX6D))) {
91 reg &= 0xff; /* mx6 silicon revision */
92 return (type << 12) | (reg + (0x10 * (major + 1)));
96 * OCOTP_CFG3[17:16] (see Fusemap Description Table offset 0x440)
97 * defines a 2-bit SPEED_GRADING
99 #define OCOTP_CFG3_SPEED_SHIFT 16
100 #define OCOTP_CFG3_SPEED_800MHZ 0
101 #define OCOTP_CFG3_SPEED_850MHZ 1
102 #define OCOTP_CFG3_SPEED_1GHZ 2
103 #define OCOTP_CFG3_SPEED_1P2GHZ 3
105 u32 get_cpu_speed_grade_hz(void)
107 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
108 struct fuse_bank *bank = &ocotp->bank[0];
109 struct fuse_bank0_regs *fuse =
110 (struct fuse_bank0_regs *)bank->fuse_regs;
113 val = readl(&fuse->cfg3);
114 val >>= OCOTP_CFG3_SPEED_SHIFT;
118 /* Valid for IMX6DQ */
119 case OCOTP_CFG3_SPEED_1P2GHZ:
120 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
122 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
123 case OCOTP_CFG3_SPEED_1GHZ:
125 /* Valid for IMX6DQ */
126 case OCOTP_CFG3_SPEED_850MHZ:
127 if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
129 /* Valid for IMX6SX/IMX6SDL/IMX6DQ */
130 case OCOTP_CFG3_SPEED_800MHZ:
137 * OCOTP_MEM0[7:6] (see Fusemap Description Table offset 0x480)
138 * defines a 2-bit Temperature Grade
140 * return temperature grade and min/max temperature in celcius
142 #define OCOTP_MEM0_TEMP_SHIFT 6
144 u32 get_cpu_temp_grade(int *minc, int *maxc)
146 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
147 struct fuse_bank *bank = &ocotp->bank[1];
148 struct fuse_bank1_regs *fuse =
149 (struct fuse_bank1_regs *)bank->fuse_regs;
152 val = readl(&fuse->mem0);
153 val >>= OCOTP_MEM0_TEMP_SHIFT;
157 if (val == TEMP_AUTOMOTIVE) {
160 } else if (val == TEMP_INDUSTRIAL) {
163 } else if (val == TEMP_EXTCOMMERCIAL) {
174 #ifdef CONFIG_REVISION_TAG
175 u32 __weak get_board_rev(void)
177 u32 cpurev = get_cpu_rev();
178 u32 type = ((cpurev >> 12) & 0xff);
179 if (type == MXC_CPU_MX6SOLO)
180 cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
182 if (type == MXC_CPU_MX6D)
183 cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
191 struct aipstz_regs *aips1, *aips2;
193 struct aipstz_regs *aips3;
196 aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
197 aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
199 aips3 = (struct aipstz_regs *)AIPS3_CONFIG_BASE_ADDR;
203 * Set all MPROTx to be non-bufferable, trusted for R/W,
204 * not forced to user-mode.
206 writel(0x77777777, &aips1->mprot0);
207 writel(0x77777777, &aips1->mprot1);
208 writel(0x77777777, &aips2->mprot0);
209 writel(0x77777777, &aips2->mprot1);
212 * Set all OPACRx to be non-bufferable, not require
213 * supervisor privilege level for access,allow for
214 * write access and untrusted master access.
216 writel(0x00000000, &aips1->opacr0);
217 writel(0x00000000, &aips1->opacr1);
218 writel(0x00000000, &aips1->opacr2);
219 writel(0x00000000, &aips1->opacr3);
220 writel(0x00000000, &aips1->opacr4);
221 writel(0x00000000, &aips2->opacr0);
222 writel(0x00000000, &aips2->opacr1);
223 writel(0x00000000, &aips2->opacr2);
224 writel(0x00000000, &aips2->opacr3);
225 writel(0x00000000, &aips2->opacr4);
229 * Set all MPROTx to be non-bufferable, trusted for R/W,
230 * not forced to user-mode.
232 writel(0x77777777, &aips3->mprot0);
233 writel(0x77777777, &aips3->mprot1);
236 * Set all OPACRx to be non-bufferable, not require
237 * supervisor privilege level for access,allow for
238 * write access and untrusted master access.
240 writel(0x00000000, &aips3->opacr0);
241 writel(0x00000000, &aips3->opacr1);
242 writel(0x00000000, &aips3->opacr2);
243 writel(0x00000000, &aips3->opacr3);
244 writel(0x00000000, &aips3->opacr4);
248 static void clear_ldo_ramp(void)
250 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
253 /* ROM may modify LDO ramp up time according to fuse setting, so in
254 * order to be in the safe side we neeed to reset these settings to
255 * match the reset value: 0'b00
257 reg = readl(&anatop->ana_misc2);
258 reg &= ~(0x3f << 24);
259 writel(reg, &anatop->ana_misc2);
263 * Set the PMU_REG_CORE register
265 * Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
266 * Possible values are from 0.725V to 1.450V in steps of
269 static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
271 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
272 u32 val, step, old, reg = readl(&anatop->reg_core);
276 val = 0x00; /* Power gated off */
278 val = 0x1F; /* Power FET switched full on. No regulation */
280 val = (mv - 700) / 25;
298 old = (reg & (0x1F << shift)) >> shift;
299 step = abs(val - old);
303 reg = (reg & ~(0x1F << shift)) | (val << shift);
304 writel(reg, &anatop->reg_core);
307 * The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
315 static void imx_set_wdog_powerdown(bool enable)
317 struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
318 struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
321 struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
322 writew(enable, &wdog3->wmcr);
325 /* Write to the PDE (Power Down Enable) bit */
326 writew(enable, &wdog1->wmcr);
327 writew(enable, &wdog2->wmcr);
330 static void set_ahb_rate(u32 val)
332 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
335 div = get_periph_clk() / val - 1;
336 reg = readl(&mxc_ccm->cbcdr);
338 writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
339 (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
342 static void clear_mmdc_ch_mask(void)
344 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
346 /* Clear MMDC channel mask */
347 writel(0, &mxc_ccm->ccdr);
350 static void init_bandgap(void)
352 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
354 * Ensure the bandgap has stabilized.
356 while (!(readl(&anatop->ana_misc0) & 0x80))
359 * For best noise performance of the analog blocks using the
360 * outputs of the bandgap, the reftop_selfbiasoff bit should
363 writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set);
368 static void set_preclk_from_osc(void)
370 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
373 reg = readl(&mxc_ccm->cscmr1);
374 reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
375 writel(reg, &mxc_ccm->cscmr1);
379 #define SRC_SCR_WARM_RESET_ENABLE 0
381 static void init_src(void)
383 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
387 * force warm reset sources to generate cold reset
388 * for a more reliable restart
390 val = readl(&src_regs->scr);
391 val &= ~(1 << SRC_SCR_WARM_RESET_ENABLE);
392 writel(val, &src_regs->scr);
395 int arch_cpu_init(void)
399 /* Need to clear MMDC_CHx_MASK to make warm reset work. */
400 clear_mmdc_ch_mask();
403 * Disable self-bias circuit in the analog bandap.
404 * The self-bias circuit is used by the bandgap during startup.
405 * This bit should be set after the bandgap has initialized.
410 * When low freq boot is enabled, ROM will not set AHB
411 * freq, so we need to ensure AHB freq is 132MHz in such
414 if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
415 set_ahb_rate(132000000);
417 /* Set perclk to source from OSC 24MHz */
418 #if defined(CONFIG_MX6SL)
419 set_preclk_from_osc();
422 imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
424 #ifdef CONFIG_APBH_DMA
434 int board_postclk_init(void)
436 set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
441 #ifndef CONFIG_SYS_DCACHE_OFF
442 void enable_caches(void)
444 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
445 enum dcache_option option = DCACHE_WRITETHROUGH;
447 enum dcache_option option = DCACHE_WRITEBACK;
450 /* Avoid random hang when download by usb */
451 invalidate_dcache_all();
453 /* Enable D-cache. I-cache is already enabled in start.S */
456 /* Enable caching on OCRAM and ROM */
457 mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
460 mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
466 #if defined(CONFIG_FEC_MXC)
467 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
469 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
470 struct fuse_bank *bank = &ocotp->bank[4];
471 struct fuse_bank4_regs *fuse =
472 (struct fuse_bank4_regs *)bank->fuse_regs;
474 u32 value = readl(&fuse->mac_addr_high);
475 mac[0] = (value >> 8);
478 value = readl(&fuse->mac_addr_low);
479 mac[2] = value >> 24 ;
480 mac[3] = value >> 16 ;
481 mac[4] = value >> 8 ;
487 void boot_mode_apply(unsigned cfg_val)
490 struct src *psrc = (struct src *)SRC_BASE_ADDR;
491 writel(cfg_val, &psrc->gpr9);
492 reg = readl(&psrc->gpr10);
497 writel(reg, &psrc->gpr10);
500 * cfg_val will be used for
501 * Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
502 * After reset, if GPR10[28] is 1, ROM will use GPR9[25:0]
503 * instead of SBMR1 to determine the boot device.
505 const struct boot_mode soc_boot_modes[] = {
506 {"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
507 /* reserved value should start rom usb */
508 {"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
509 {"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
510 {"ecspi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
511 {"ecspi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
512 {"ecspi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
513 {"ecspi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
514 /* 4 bit bus width */
515 {"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
516 {"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
517 {"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
518 {"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
524 struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
525 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
528 u32 reg, periph1, periph2;
530 if (is_cpu_type(MXC_CPU_MX6SX))
533 /* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
534 * to make sure PFD is working right, otherwise, PFDs may
535 * not output clock after reset, MX6DL and MX6SL have added 396M pfd
536 * workaround in ROM code, as bus clock need it
539 mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
540 ANATOP_PFD_CLKGATE_MASK(1) |
541 ANATOP_PFD_CLKGATE_MASK(2) |
542 ANATOP_PFD_CLKGATE_MASK(3);
543 mask528 = ANATOP_PFD_CLKGATE_MASK(1) |
544 ANATOP_PFD_CLKGATE_MASK(3);
546 reg = readl(&ccm->cbcmr);
547 periph2 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK)
548 >> MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET);
549 periph1 = ((reg & MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
550 >> MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET);
552 /* Checking if PLL2 PFD0 or PLL2 PFD2 is using for periph clock */
553 if ((periph2 != 0x2) && (periph1 != 0x2))
554 mask528 |= ANATOP_PFD_CLKGATE_MASK(0);
556 if ((periph2 != 0x1) && (periph1 != 0x1) &&
557 (periph2 != 0x3) && (periph1 != 0x3))
558 mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
560 writel(mask480, &anatop->pfd_480_set);
561 writel(mask528, &anatop->pfd_528_set);
562 writel(mask480, &anatop->pfd_480_clr);
563 writel(mask528, &anatop->pfd_528_clr);
566 #ifdef CONFIG_IMX_HDMI
567 void imx_enable_hdmi_phy(void)
569 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
571 reg = readb(&hdmi->phy_conf0);
572 reg |= HDMI_PHY_CONF0_PDZ_MASK;
573 writeb(reg, &hdmi->phy_conf0);
575 reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
576 writeb(reg, &hdmi->phy_conf0);
578 reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
579 writeb(reg, &hdmi->phy_conf0);
580 writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
583 void imx_setup_hdmi(void)
585 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
586 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
589 /* Turn on HDMI PHY clock */
590 reg = readl(&mxc_ccm->CCGR2);
591 reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
592 MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
593 writel(reg, &mxc_ccm->CCGR2);
594 writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
595 reg = readl(&mxc_ccm->chsccdr);
596 reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
597 MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
598 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
599 reg |= (CHSCCDR_PODF_DIVIDE_BY_3
600 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
601 |(CHSCCDR_IPU_PRE_CLK_540M_PFD
602 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
603 writel(reg, &mxc_ccm->chsccdr);
607 #ifndef CONFIG_SYS_L2CACHE_OFF
608 #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
609 void v7_outer_cache_enable(void)
611 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
616 * Set bit 22 in the auxiliary control register. If this bit
617 * is cleared, PL310 treats Normal Shared Non-cacheable
618 * accesses as Cacheable no-allocate.
620 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
622 #if defined CONFIG_MX6SL
623 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
624 val = readl(&iomux->gpr[11]);
625 if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
626 /* L2 cache configured as OCRAM, reset it */
627 val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
628 writel(val, &iomux->gpr[11]);
632 /* Must disable the L2 before changing the latency parameters */
633 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
635 writel(0x132, &pl310->pl310_tag_latency_ctrl);
636 writel(0x132, &pl310->pl310_data_latency_ctrl);
638 val = readl(&pl310->pl310_prefetch_ctrl);
640 /* Turn on the L2 I/D prefetch */
644 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
645 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
646 * But according to ARM PL310 errata: 752271
647 * ID: 752271: Double linefill feature can cause data corruption
648 * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
649 * Workaround: The only workaround to this erratum is to disable the
650 * double linefill feature. This is the default behavior.
656 writel(val, &pl310->pl310_prefetch_ctrl);
658 val = readl(&pl310->pl310_power_ctrl);
659 val |= L2X0_DYNAMIC_CLK_GATING_EN;
660 val |= L2X0_STNDBY_MODE_EN;
661 writel(val, &pl310->pl310_power_ctrl);
663 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
666 void v7_outer_cache_disable(void)
668 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
670 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
672 #endif /* !CONFIG_SYS_L2CACHE_OFF */