3 * Clock initialization for OMAP4
6 * Texas Instruments, <www.ti.com>
8 * Aneesh V <aneesh@ti.com>
10 * Based on previous work by:
11 * Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * Rajendra Nayak <rnayak@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/omap_common.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/utils.h>
38 #include <asm/omap_gpio.h>
41 #ifndef CONFIG_SPL_BUILD
43 * printing to console doesn't work unless
44 * this code is executed from SPL
46 #define printf(fmt, args...)
50 const u32 sys_clk_array[8] = {
51 12000000, /* 12 MHz */
52 13000000, /* 13 MHz */
53 16800000, /* 16.8 MHz */
54 19200000, /* 19.2 MHz */
55 26000000, /* 26 MHz */
56 27000000, /* 27 MHz */
57 38400000, /* 38.4 MHz */
60 static inline u32 __get_sys_clk_index(void)
64 * For ES1 the ROM code calibration of sys clock is not reliable
65 * due to hw issue. So, use hard-coded value. If this value is not
66 * correct for any board over-ride this function in board file
67 * From ES2.0 onwards you will get this information from
70 if (omap_revision() == OMAP4430_ES1_0)
71 ind = OMAP_SYS_CLK_IND_38_4_MHZ;
73 /* SYS_CLKSEL - 1 to match the dpll param array indices */
74 ind = (readl((*prcm)->cm_sys_clksel) &
75 CM_SYS_CLKSEL_SYS_CLKSEL_MASK) - 1;
80 u32 get_sys_clk_index(void)
81 __attribute__ ((weak, alias("__get_sys_clk_index")));
83 u32 get_sys_clk_freq(void)
85 u8 index = get_sys_clk_index();
86 return sys_clk_array[index];
89 void setup_post_dividers(u32 const base, const struct dpll_params *params)
91 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
93 /* Setup post-dividers */
95 writel(params->m2, &dpll_regs->cm_div_m2_dpll);
97 writel(params->m3, &dpll_regs->cm_div_m3_dpll);
98 if (params->m4_h11 >= 0)
99 writel(params->m4_h11, &dpll_regs->cm_div_m4_h11_dpll);
100 if (params->m5_h12 >= 0)
101 writel(params->m5_h12, &dpll_regs->cm_div_m5_h12_dpll);
102 if (params->m6_h13 >= 0)
103 writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll);
104 if (params->m7_h14 >= 0)
105 writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
106 if (params->h22 >= 0)
107 writel(params->h22, &dpll_regs->cm_div_h22_dpll);
108 if (params->h23 >= 0)
109 writel(params->h23, &dpll_regs->cm_div_h23_dpll);
112 static inline void do_bypass_dpll(u32 const base)
114 struct dpll_regs *dpll_regs = (struct dpll_regs *)base;
116 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
117 CM_CLKMODE_DPLL_DPLL_EN_MASK,
118 DPLL_EN_FAST_RELOCK_BYPASS <<
119 CM_CLKMODE_DPLL_EN_SHIFT);
122 static inline void wait_for_bypass(u32 const base)
124 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
126 if (!wait_on_value(ST_DPLL_CLK_MASK, 0, &dpll_regs->cm_idlest_dpll,
128 printf("Bypassing DPLL failed %x\n", base);
132 static inline void do_lock_dpll(u32 const base)
134 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
136 clrsetbits_le32(&dpll_regs->cm_clkmode_dpll,
137 CM_CLKMODE_DPLL_DPLL_EN_MASK,
138 DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
141 static inline void wait_for_lock(u32 const base)
143 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
145 if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
146 &dpll_regs->cm_idlest_dpll, LDELAY)) {
147 printf("DPLL locking failed for %x\n", base);
152 inline u32 check_for_lock(u32 const base)
154 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
155 u32 lock = readl(&dpll_regs->cm_idlest_dpll) & ST_DPLL_CLK_MASK;
160 const struct dpll_params *get_mpu_dpll_params(struct dplls const *dpll_data)
162 u32 sysclk_ind = get_sys_clk_index();
163 return &dpll_data->mpu[sysclk_ind];
166 const struct dpll_params *get_core_dpll_params(struct dplls const *dpll_data)
168 u32 sysclk_ind = get_sys_clk_index();
169 return &dpll_data->core[sysclk_ind];
172 const struct dpll_params *get_per_dpll_params(struct dplls const *dpll_data)
174 u32 sysclk_ind = get_sys_clk_index();
175 return &dpll_data->per[sysclk_ind];
178 const struct dpll_params *get_iva_dpll_params(struct dplls const *dpll_data)
180 u32 sysclk_ind = get_sys_clk_index();
181 return &dpll_data->iva[sysclk_ind];
184 const struct dpll_params *get_usb_dpll_params(struct dplls const *dpll_data)
186 u32 sysclk_ind = get_sys_clk_index();
187 return &dpll_data->usb[sysclk_ind];
190 const struct dpll_params *get_abe_dpll_params(struct dplls const *dpll_data)
192 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
193 u32 sysclk_ind = get_sys_clk_index();
194 return &dpll_data->abe[sysclk_ind];
196 return dpll_data->abe;
200 static void do_setup_dpll(u32 const base, const struct dpll_params *params,
204 struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
206 temp = readl(&dpll_regs->cm_clksel_dpll);
208 if (check_for_lock(base)) {
210 * The Dpll has already been locked by rom code using CH.
211 * Check if M,N are matching with Ideal nominal opp values.
212 * If matches, skip the rest otherwise relock.
214 M = (temp & CM_CLKSEL_DPLL_M_MASK) >> CM_CLKSEL_DPLL_M_SHIFT;
215 N = (temp & CM_CLKSEL_DPLL_N_MASK) >> CM_CLKSEL_DPLL_N_SHIFT;
216 if ((M != (params->m)) || (N != (params->n))) {
217 debug("\n %s Dpll locked, but not for ideal M = %d,"
218 "N = %d values, current values are M = %d,"
219 "N= %d" , dpll, params->m, params->n,
222 /* Dpll locked with ideal values for nominal opps. */
223 debug("\n %s Dpll already locked with ideal"
224 "nominal opp values", dpll);
225 goto setup_post_dividers;
232 temp &= ~CM_CLKSEL_DPLL_M_MASK;
233 temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
235 temp &= ~CM_CLKSEL_DPLL_N_MASK;
236 temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
238 writel(temp, &dpll_regs->cm_clksel_dpll);
245 setup_post_dividers(base, params);
247 /* Wait till the DPLL locks */
252 u32 omap_ddr_clk(void)
254 u32 ddr_clk, sys_clk_khz, omap_rev, divider;
255 const struct dpll_params *core_dpll_params;
257 omap_rev = omap_revision();
258 sys_clk_khz = get_sys_clk_freq() / 1000;
260 core_dpll_params = get_core_dpll_params(*dplls_data);
262 debug("sys_clk %d\n ", sys_clk_khz * 1000);
264 /* Find Core DPLL locked frequency first */
265 ddr_clk = sys_clk_khz * 2 * core_dpll_params->m /
266 (core_dpll_params->n + 1);
268 if (omap_rev < OMAP5430_ES1_0) {
270 * DDR frequency is PHY_ROOT_CLK/2
271 * PHY_ROOT_CLK = Fdpll/2/M2
276 * DDR frequency is PHY_ROOT_CLK
277 * PHY_ROOT_CLK = Fdpll/2/M2
282 ddr_clk = ddr_clk / divider / core_dpll_params->m2;
283 ddr_clk *= 1000; /* convert to Hz */
284 debug("ddr_clk %d\n ", ddr_clk);
292 * Resulting MPU frequencies:
293 * 4430 ES1.0 : 600 MHz
294 * 4430 ES2.x : 792 MHz (OPP Turbo)
295 * 4460 : 920 MHz (OPP Turbo) - DCC disabled
297 void configure_mpu_dpll(void)
299 const struct dpll_params *params;
300 struct dpll_regs *mpu_dpll_regs;
302 omap_rev = omap_revision();
305 * DCC and clock divider settings for 4460.
306 * DCC is required, if more than a certain frequency is required.
310 if ((omap_rev >= OMAP4460_ES1_0) && (omap_rev < OMAP5430_ES1_0)) {
312 (struct dpll_regs *)((*prcm)->cm_clkmode_dpll_mpu);
313 bypass_dpll((*prcm)->cm_clkmode_dpll_mpu);
314 clrbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
315 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
316 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
317 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
318 clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
319 CM_CLKSEL_DCC_EN_MASK);
322 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
323 MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
324 setbits_le32((*prcm)->cm_mpu_mpu_clkctrl,
325 MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
327 params = get_mpu_dpll_params(*dplls_data);
329 do_setup_dpll((*prcm)->cm_clkmode_dpll_mpu, params, DPLL_LOCK, "mpu");
330 debug("MPU DPLL locked\n");
333 #ifdef CONFIG_USB_EHCI_OMAP
334 static void setup_usb_dpll(void)
336 const struct dpll_params *params;
337 u32 sys_clk_khz, sd_div, num, den;
339 sys_clk_khz = get_sys_clk_freq() / 1000;
342 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
343 * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250)
344 * - where CLKINP is sys_clk in MHz
345 * Use CLKINP in KHz and adjust the denominator accordingly so
346 * that we have enough accuracy and at the same time no overflow
348 params = get_usb_dpll_params(*dplls_data);
349 num = params->m * sys_clk_khz;
350 den = (params->n + 1) * 250 * 1000;
353 clrsetbits_le32((*prcm)->cm_clksel_dpll_usb,
354 CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK,
355 sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT);
357 /* Now setup the dpll with the regular function */
358 do_setup_dpll((*prcm)->cm_clkmode_dpll_usb, params, DPLL_LOCK, "usb");
362 static void setup_dplls(void)
365 const struct dpll_params *params;
367 debug("setup_dplls\n");
370 params = get_core_dpll_params(*dplls_data); /* default - safest */
372 * Do not lock the core DPLL now. Just set it up.
373 * Core DPLL will be locked after setting up EMIF
374 * using the FREQ_UPDATE method(freq_update_core())
376 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
377 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
378 DPLL_NO_LOCK, "core");
380 do_setup_dpll((*prcm)->cm_clkmode_dpll_core, params,
382 /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */
383 temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) |
384 (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) |
385 (CLKSEL_L4_L3_DIV_2 << CLKSEL_L4_SHIFT);
386 writel(temp, (*prcm)->cm_clksel_core);
387 debug("Core DPLL configured\n");
390 params = get_per_dpll_params(*dplls_data);
391 do_setup_dpll((*prcm)->cm_clkmode_dpll_per,
392 params, DPLL_LOCK, "per");
393 debug("PER DPLL locked\n");
396 configure_mpu_dpll();
398 #ifdef CONFIG_USB_EHCI_OMAP
403 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
404 static void setup_non_essential_dplls(void)
407 const struct dpll_params *params;
410 clrsetbits_le32((*prcm)->cm_bypclk_dpll_iva,
411 CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2);
413 params = get_iva_dpll_params(*dplls_data);
414 do_setup_dpll((*prcm)->cm_clkmode_dpll_iva, params, DPLL_LOCK, "iva");
416 /* Configure ABE dpll */
417 params = get_abe_dpll_params(*dplls_data);
418 #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
419 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK;
421 abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK;
423 * We need to enable some additional options to achieve
424 * 196.608MHz from 32768 Hz
426 setbits_le32((*prcm)->cm_clkmode_dpll_abe,
427 CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK|
428 CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK|
429 CM_CLKMODE_DPLL_LPMODE_EN_MASK|
430 CM_CLKMODE_DPLL_REGM4XEN_MASK);
431 /* Spend 4 REFCLK cycles at each stage */
432 clrsetbits_le32((*prcm)->cm_clkmode_dpll_abe,
433 CM_CLKMODE_DPLL_RAMP_RATE_MASK,
434 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT);
437 /* Select the right reference clk */
438 clrsetbits_le32((*prcm)->cm_abe_pll_ref_clksel,
439 CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK,
440 abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT);
442 do_setup_dpll((*prcm)->cm_clkmode_dpll_abe, params, DPLL_LOCK, "abe");
446 void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv)
451 /* See if we can first get the GPIO if needed */
453 ret = gpio_request(gpio, "TPS62361_VSEL0_GPIO");
455 printf("%s: gpio %d request failed %d\n", __func__, gpio, ret);
459 /* Pull the GPIO low to select SET0 register, while we program SET1 */
461 gpio_direction_output(gpio, 0);
463 step = volt_mv - TPS62361_BASE_VOLT_MV;
466 debug("do_scale_tps62361: volt - %d step - 0x%x\n", volt_mv, step);
467 if (omap_vc_bypass_send_value(TPS62361_I2C_SLAVE_ADDR, reg, step))
468 puts("Scaling voltage failed for vdd_mpu from TPS\n");
470 /* Pull the GPIO high to select SET1 register */
472 gpio_direction_output(gpio, 1);
475 void do_scale_vcore(u32 vcore_reg, u32 volt_mv)
478 u32 offset = volt_mv;
480 /* convert to uV for better accuracy in the calculations */
483 offset_code = get_offset_code(offset);
485 debug("do_scale_vcore: volt - %d offset_code - 0x%x\n", volt_mv,
488 if (omap_vc_bypass_send_value(SMPS_I2C_SLAVE_ADDR,
489 vcore_reg, offset_code))
490 printf("Scaling voltage failed for 0x%x\n", vcore_reg);
493 static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode)
495 clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
496 enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
497 debug("Enable clock domain - %x\n", clkctrl_reg);
500 static inline void wait_for_clk_enable(u32 clkctrl_addr)
502 u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
505 while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
506 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
508 clkctrl = readl(clkctrl_addr);
509 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
510 MODULE_CLKCTRL_IDLEST_SHIFT;
512 printf("Clock enable failed for 0x%x idlest 0x%x\n",
513 clkctrl_addr, clkctrl);
519 static inline void enable_clock_module(u32 const clkctrl_addr, u32 enable_mode,
522 clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
523 enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
524 debug("Enable clock module - %x\n", clkctrl_addr);
526 wait_for_clk_enable(clkctrl_addr);
529 void freq_update_core(void)
531 u32 freq_config1 = 0;
532 const struct dpll_params *core_dpll_params;
533 u32 omap_rev = omap_revision();
535 core_dpll_params = get_core_dpll_params(*dplls_data);
536 /* Put EMIF clock domain in sw wakeup mode */
537 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
538 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
539 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
540 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
542 freq_config1 = SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK |
543 SHADOW_FREQ_CONFIG1_DLL_RESET_MASK;
545 freq_config1 |= (DPLL_EN_LOCK << SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT) &
546 SHADOW_FREQ_CONFIG1_DPLL_EN_MASK;
548 freq_config1 |= (core_dpll_params->m2 <<
549 SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT) &
550 SHADOW_FREQ_CONFIG1_M2_DIV_MASK;
552 writel(freq_config1, (*prcm)->cm_shadow_freq_config1);
553 if (!wait_on_value(SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK, 0,
554 (u32 *) (*prcm)->cm_shadow_freq_config1, LDELAY)) {
555 puts("FREQ UPDATE procedure failed!!");
560 * Putting EMIF in HW_AUTO is seen to be causing issues with
561 * EMIF clocks and the master DLL. Put EMIF in SW_WKUP
562 * in OMAP5430 ES1.0 silicon
564 if (omap_rev != OMAP5430_ES1_0) {
565 /* Put EMIF clock domain back in hw auto mode */
566 enable_clock_domain((*prcm)->cm_memif_clkstctrl,
567 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
568 wait_for_clk_enable((*prcm)->cm_memif_emif_1_clkctrl);
569 wait_for_clk_enable((*prcm)->cm_memif_emif_2_clkctrl);
573 void bypass_dpll(u32 const base)
575 do_bypass_dpll(base);
576 wait_for_bypass(base);
579 void lock_dpll(u32 const base)
585 void setup_clocks_for_console(void)
587 /* Do not add any spl_debug prints in this function */
588 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
589 CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
590 CD_CLKCTRL_CLKTRCTRL_SHIFT);
592 /* Enable all UARTs - console will be on one of them */
593 clrsetbits_le32((*prcm)->cm_l4per_uart1_clkctrl,
594 MODULE_CLKCTRL_MODULEMODE_MASK,
595 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
596 MODULE_CLKCTRL_MODULEMODE_SHIFT);
598 clrsetbits_le32((*prcm)->cm_l4per_uart2_clkctrl,
599 MODULE_CLKCTRL_MODULEMODE_MASK,
600 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
601 MODULE_CLKCTRL_MODULEMODE_SHIFT);
603 clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
604 MODULE_CLKCTRL_MODULEMODE_MASK,
605 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
606 MODULE_CLKCTRL_MODULEMODE_SHIFT);
608 clrsetbits_le32((*prcm)->cm_l4per_uart3_clkctrl,
609 MODULE_CLKCTRL_MODULEMODE_MASK,
610 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
611 MODULE_CLKCTRL_MODULEMODE_SHIFT);
613 clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
614 CD_CLKCTRL_CLKTRCTRL_HW_AUTO <<
615 CD_CLKCTRL_CLKTRCTRL_SHIFT);
618 void do_enable_clocks(u32 const *clk_domains,
619 u32 const *clk_modules_hw_auto,
620 u32 const *clk_modules_explicit_en,
625 /* Put the clock domains in SW_WKUP mode */
626 for (i = 0; (i < max) && clk_domains[i]; i++) {
627 enable_clock_domain(clk_domains[i],
628 CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
631 /* Clock modules that need to be put in HW_AUTO */
632 for (i = 0; (i < max) && clk_modules_hw_auto[i]; i++) {
633 enable_clock_module(clk_modules_hw_auto[i],
634 MODULE_CLKCTRL_MODULEMODE_HW_AUTO,
638 /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
639 for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
640 enable_clock_module(clk_modules_explicit_en[i],
641 MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
645 /* Put the clock domains in HW_AUTO mode now */
646 for (i = 0; (i < max) && clk_domains[i]; i++) {
647 enable_clock_domain(clk_domains[i],
648 CD_CLKCTRL_CLKTRCTRL_HW_AUTO);
654 switch (omap_hw_init_context()) {
655 case OMAP_INIT_CONTEXT_SPL:
656 case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
657 case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
658 enable_basic_clocks();
661 #ifdef CONFIG_SYS_CLOCKS_ENABLE_ALL
662 setup_non_essential_dplls();
663 enable_non_essential_clocks();
670 if (OMAP_INIT_CONTEXT_SPL != omap_hw_init_context())
671 enable_basic_uboot_clocks();