5 * Texas Instruments, <www.ti.com>
7 * Aneesh V <aneesh@ti.com>
9 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/omap_common.h>
17 #include <asm/utils.h>
18 #include <linux/compiler.h>
20 static int emif1_enabled = -1, emif2_enabled = -1;
22 void set_lpmode_selfrefresh(u32 base)
24 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
27 reg = readl(&emif->emif_pwr_mgmt_ctrl);
28 reg &= ~EMIF_REG_LP_MODE_MASK;
29 reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
30 reg &= ~EMIF_REG_SR_TIM_MASK;
31 writel(reg, &emif->emif_pwr_mgmt_ctrl);
33 /* dummy read for the new SR_TIM to be loaded */
34 readl(&emif->emif_pwr_mgmt_ctrl);
37 void force_emif_self_refresh()
39 set_lpmode_selfrefresh(EMIF1_BASE);
41 set_lpmode_selfrefresh(EMIF2_BASE);
44 inline u32 emif_num(u32 base)
46 if (base == EMIF1_BASE)
48 else if (base == EMIF2_BASE)
54 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
57 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
59 mr_addr |= cs << EMIF_REG_CS_SHIFT;
60 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
61 if (omap_revision() == OMAP4430_ES2_0)
62 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
64 mr = readl(&emif->emif_lpddr2_mode_reg_data);
65 debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
67 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
68 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
69 ((mr & 0xff000000) >> 24) == (mr & 0xff))
75 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
77 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
79 mr_addr |= cs << EMIF_REG_CS_SHIFT;
80 writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
81 writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
84 void emif_reset_phy(u32 base)
86 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
89 iodft = readl(&emif->emif_iodft_tlgc);
90 iodft |= EMIF_REG_RESET_PHY_MASK;
91 writel(iodft, &emif->emif_iodft_tlgc);
94 static void do_lpddr2_init(u32 base, u32 cs)
97 const struct lpddr2_mr_regs *mr_regs;
99 get_lpddr2_mr_regs(&mr_regs);
100 /* Wait till device auto initialization is complete */
101 while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
103 set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
106 * Enough loops assuming a maximum of 2GHz
111 set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
112 set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
115 * Enable refresh along with writing MR2
116 * Encoding of RL in MR2 is (RL - 2)
118 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
119 set_mr(base, cs, mr_addr, mr_regs->mr2);
121 if (mr_regs->mr3 > 0)
122 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
125 static void lpddr2_init(u32 base, const struct emif_regs *regs)
127 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
130 clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
133 * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
134 * when EMIF_SDRAM_CONFIG register is written
136 setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
139 * Set the SDRAM_CONFIG and PHY_CTRL for the
140 * un-locked frequency & default RL
142 writel(regs->sdram_config_init, &emif->emif_sdram_config);
143 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
145 do_ext_phy_settings(base, regs);
147 do_lpddr2_init(base, CS0);
148 if (regs->sdram_config & EMIF_REG_EBANK_MASK)
149 do_lpddr2_init(base, CS1);
151 writel(regs->sdram_config, &emif->emif_sdram_config);
152 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
154 /* Enable refresh now */
155 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
159 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
163 void emif_update_timings(u32 base, const struct emif_regs *regs)
165 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
168 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
170 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl_shdw);
172 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
173 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
174 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
175 if (omap_revision() == OMAP4430_ES1_0) {
176 /* ES1 bug EMIF should be in force idle during freq_update */
177 writel(0, &emif->emif_pwr_mgmt_ctrl);
179 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
180 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
182 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
183 writel(regs->zq_config, &emif->emif_zq_config);
184 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
185 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
187 if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
188 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
189 &emif->emif_l3_config);
190 } else if (omap_revision() >= OMAP4460_ES1_0) {
191 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
192 &emif->emif_l3_config);
194 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
195 &emif->emif_l3_config);
199 #ifndef CONFIG_OMAP44XX
200 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
202 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
204 /* keep sdram in self-refresh */
205 writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
206 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
210 * Set invert_clkout (if activated)--DDR_PHYCTRL_1
211 * Invert clock adds an additional half cycle delay on the
212 * command interface. The additional half cycle, is usually
213 * meant to enable leveling in the situation that DQS is later
214 * than CK on the board.It also helps provide some additional
215 * margin for leveling.
217 writel(regs->emif_ddr_phy_ctlr_1,
218 &emif->emif_ddr_phy_ctrl_1);
220 writel(regs->emif_ddr_phy_ctlr_1,
221 &emif->emif_ddr_phy_ctrl_1_shdw);
224 writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
225 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
227 /* Launch Full leveling */
228 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
230 /* Wait till full leveling is complete */
231 readl(&emif->emif_rd_wr_lvl_ctl);
234 /* Read data eye leveling no of samples */
235 config_data_eye_leveling_samples(base);
238 * Launch 8 incremental WR_LVL- to compensate for
241 writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
242 &emif->emif_rd_wr_lvl_ctl);
246 /* Launch Incremental leveling */
247 writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
251 static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
253 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
254 u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
257 emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
258 phy = readl(&emif->emif_ddr_phy_ctrl_1);
260 /* Update PHY_REG_RDDQS_RATIO */
261 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
262 if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK))
263 for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
264 reg = readl(emif_phy_status++);
265 writel(reg, emif_ext_phy_ctrl_reg++);
266 writel(reg, emif_ext_phy_ctrl_reg++);
269 /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
270 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
271 emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12];
272 if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
273 for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
274 reg = readl(emif_phy_status++);
275 writel(reg, emif_ext_phy_ctrl_reg++);
276 writel(reg, emif_ext_phy_ctrl_reg++);
279 /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
280 emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
281 emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17];
282 if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
283 for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
284 reg = readl(emif_phy_status++);
285 writel(reg, emif_ext_phy_ctrl_reg++);
286 writel(reg, emif_ext_phy_ctrl_reg++);
289 /* Disable Leveling */
290 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
291 writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
292 writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
295 static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
297 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
299 /* Clear Error Status */
300 clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36,
301 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
302 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
304 clrsetbits_le32(&emif->emif_ddr_ext_phy_ctrl_36_shdw,
305 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR,
306 EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
308 /* Disable refreshed before leveling */
309 clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
310 EMIF_REG_INITREF_DIS_MASK);
312 /* Start Full leveling */
313 writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
317 /* Check for leveling timeout */
318 if (readl(&emif->emif_status) & EMIF_REG_LEVELING_TO_MASK) {
319 printf("Leveling timeout on EMIF%d\n", emif_num(base));
323 /* Enable refreshes after leveling */
324 clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
326 debug("HW leveling success\n");
328 * Update slave ratios in EXT_PHY_CTRLx registers
329 * as per HW leveling output
331 update_hwleveling_output(base, regs);
334 static void dra7_ddr3_init(u32 base, const struct emif_regs *regs)
336 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
339 emif_reset_phy(base);
340 writel(0x0, &emif->emif_pwr_mgmt_ctrl);
342 do_ext_phy_settings(base, regs);
344 writel(regs->ref_ctrl | EMIF_REG_INITREF_DIS_MASK,
345 &emif->emif_sdram_ref_ctrl);
346 /* Update timing registers */
347 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
348 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
349 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
351 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config);
352 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
353 writel(regs->zq_config, &emif->emif_zq_config);
354 writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
355 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
356 writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
358 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
359 writel(regs->emif_rd_wr_exec_thresh, &emif->emif_rd_wr_exec_thresh);
361 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
363 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
364 writel(regs->sdram_config_init, &emif->emif_sdram_config);
368 writel(regs->ref_ctrl_final, &emif->emif_sdram_ref_ctrl);
370 if (regs->emif_rd_wr_lvl_rmp_ctl & EMIF_REG_RDWRLVL_EN_MASK)
371 dra7_ddr3_leveling(base, regs);
374 static void omap5_ddr3_init(u32 base, const struct emif_regs *regs)
376 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
378 writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
379 writel(regs->sdram_config_init, &emif->emif_sdram_config);
381 * Set SDRAM_CONFIG and PHY control registers to locked frequency
382 * and RL =7. As the default values of the Mode Registers are not
383 * defined, contents of mode Registers must be fully initialized.
384 * H/W takes care of this initialization
386 writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
388 /* Update timing registers */
389 writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
390 writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
391 writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
393 writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
395 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
396 writel(regs->sdram_config_init, &emif->emif_sdram_config);
397 do_ext_phy_settings(base, regs);
399 writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
400 omap5_ddr3_leveling(base, regs);
403 static void ddr3_init(u32 base, const struct emif_regs *regs)
406 omap5_ddr3_init(base, regs);
408 dra7_ddr3_init(base, regs);
412 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
413 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
416 * Organization and refresh requirements for LPDDR2 devices of different
417 * types and densities. Derived from JESD209-2 section 2.4
419 const struct lpddr2_addressing addressing_table[] = {
420 /* Banks tREFIx10 rowx32,rowx16 colx32,colx16 density */
421 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
422 {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
423 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
424 {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
425 {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
426 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
427 {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
428 {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
429 {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
430 {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
433 static const u32 lpddr2_density_2_size_in_mbytes[] = {
447 * Calculate the period of DDR clock from frequency value and set the
448 * denominator and numerator in global variables for easy access later
450 static void set_ddr_clk_period(u32 freq)
454 * period_in_ns = 10^9/freq
458 cancel_out(T_num, T_den, 200);
463 * Convert time in nano seconds to number of cycles of DDR clock
465 static inline u32 ns_2_cycles(u32 ns)
467 return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
471 * ns_2_cycles with the difference that the time passed is 2 times the actual
472 * value(to avoid fractions). The cycles returned is for the original value of
473 * the timing parameter
475 static inline u32 ns_x2_2_cycles(u32 ns)
477 return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
481 * Find addressing table index based on the device's type(S2 or S4) and
484 s8 addressing_table_index(u8 type, u8 density, u8 width)
487 if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
491 * Look at the way ADDR_TABLE_INDEX* values have been defined
492 * in emif.h compared to LPDDR2_DENSITY_* values
493 * The table is layed out in the increasing order of density
494 * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
497 if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
498 index = ADDR_TABLE_INDEX1GS2;
499 else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
500 index = ADDR_TABLE_INDEX2GS2;
504 debug("emif: addressing table index %d\n", index);
510 * Find the the right timing table from the array of timing
511 * tables of the device using DDR clock frequency
513 static const struct lpddr2_ac_timings *get_timings_table(const struct
514 lpddr2_ac_timings const *const *device_timings,
517 u32 i, temp, freq_nearest;
518 const struct lpddr2_ac_timings *timings = 0;
520 emif_assert(freq <= MAX_LPDDR2_FREQ);
521 emif_assert(device_timings);
524 * Start with the maximum allowed frequency - that is always safe
526 freq_nearest = MAX_LPDDR2_FREQ;
528 * Find the timings table that has the max frequency value:
529 * i. Above or equal to the DDR frequency - safe
530 * ii. The lowest that satisfies condition (i) - optimal
532 for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
533 temp = device_timings[i]->max_freq;
534 if ((temp >= freq) && (temp <= freq_nearest)) {
536 timings = device_timings[i];
539 debug("emif: timings table: %d\n", freq_nearest);
544 * Finds the value of emif_sdram_config_reg
545 * All parameters are programmed based on the device on CS0.
546 * If there is a device on CS1, it will be same as that on CS0 or
547 * it will be NVM. We don't support NVM yet.
548 * If cs1_device pointer is NULL it is assumed that there is no device
551 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
552 const struct lpddr2_device_details *cs1_device,
553 const struct lpddr2_addressing *addressing,
558 config_reg |= (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
559 config_reg |= EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
560 EMIF_REG_IBANK_POS_SHIFT;
562 config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
564 config_reg |= RL << EMIF_REG_CL_SHIFT;
566 config_reg |= addressing->row_sz[cs0_device->io_width] <<
567 EMIF_REG_ROWSIZE_SHIFT;
569 config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
571 config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
572 EMIF_REG_EBANK_SHIFT;
574 config_reg |= addressing->col_sz[cs0_device->io_width] <<
575 EMIF_REG_PAGESIZE_SHIFT;
580 static u32 get_sdram_ref_ctrl(u32 freq,
581 const struct lpddr2_addressing *addressing)
583 u32 ref_ctrl = 0, val = 0, freq_khz;
584 freq_khz = freq / 1000;
586 * refresh rate to be set is 'tREFI * freq in MHz
587 * division by 10000 to account for khz and x10 in t_REFI_us_x10
589 val = addressing->t_REFI_us_x10 * freq_khz / 10000;
590 ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
595 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
596 const struct lpddr2_min_tck *min_tck,
597 const struct lpddr2_addressing *addressing)
599 u32 tim1 = 0, val = 0;
600 val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
601 tim1 |= val << EMIF_REG_T_WTR_SHIFT;
603 if (addressing->num_banks == BANKS8)
604 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
607 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
609 tim1 |= val << EMIF_REG_T_RRD_SHIFT;
611 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
612 tim1 |= val << EMIF_REG_T_RC_SHIFT;
614 val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
615 tim1 |= val << EMIF_REG_T_RAS_SHIFT;
617 val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
618 tim1 |= val << EMIF_REG_T_WR_SHIFT;
620 val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
621 tim1 |= val << EMIF_REG_T_RCD_SHIFT;
623 val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
624 tim1 |= val << EMIF_REG_T_RP_SHIFT;
629 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
630 const struct lpddr2_min_tck *min_tck)
632 u32 tim2 = 0, val = 0;
633 val = max(min_tck->tCKE, timings->tCKE) - 1;
634 tim2 |= val << EMIF_REG_T_CKE_SHIFT;
636 val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
637 tim2 |= val << EMIF_REG_T_RTP_SHIFT;
640 * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
643 val = ns_2_cycles(timings->tXSR) - 1;
644 tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
645 tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
647 val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
648 tim2 |= val << EMIF_REG_T_XP_SHIFT;
653 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
654 const struct lpddr2_min_tck *min_tck,
655 const struct lpddr2_addressing *addressing)
657 u32 tim3 = 0, val = 0;
658 val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
659 tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
661 val = ns_2_cycles(timings->tRFCab) - 1;
662 tim3 |= val << EMIF_REG_T_RFC_SHIFT;
664 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
665 tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
667 val = ns_2_cycles(timings->tZQCS) - 1;
668 tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
670 val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
671 tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
676 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
677 const struct lpddr2_addressing *addressing,
683 EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
684 addressing->t_REFI_us_x10;
687 EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
688 addressing->t_REFI_us_x10;
689 zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
691 zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
693 zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
695 zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
698 * Assuming that two chipselects have a single calibration resistor
699 * If there are indeed two calibration resistors, then this flag should
700 * be enabled to take advantage of dual calibration feature.
701 * This data should ideally come from board files. But considering
702 * that none of the boards today have calibration resistors per CS,
703 * it would be an unnecessary overhead.
705 zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
707 zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
709 zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
714 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
715 const struct lpddr2_addressing *addressing,
718 u32 alert = 0, interval;
720 TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
723 alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
725 alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
727 alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
729 alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
731 alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
733 alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
738 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
740 u32 idle = 0, val = 0;
742 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
744 /*Maximum value in normal conditions - suggested by hw team */
746 idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
748 idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
753 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
755 u32 phy = 0, val = 0;
757 phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
759 if (freq <= 100000000)
760 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
761 else if (freq <= 200000000)
762 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
764 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
765 phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
767 /* Other fields are constant magic values. Hardcode them together */
768 phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
769 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
774 static u32 get_emif_mem_size(u32 base)
776 u32 size_mbytes = 0, temp;
777 struct emif_device_details dev_details;
778 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
779 u32 emif_nr = emif_num(base);
781 emif_reset_phy(base);
782 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
784 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
786 emif_reset_phy(base);
788 if (dev_details.cs0_device_details) {
789 temp = dev_details.cs0_device_details->density;
790 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
793 if (dev_details.cs1_device_details) {
794 temp = dev_details.cs1_device_details->density;
795 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
797 /* convert to bytes */
798 return size_mbytes << 20;
801 /* Gets the encoding corresponding to a given DMM section size */
802 u32 get_dmm_section_size_map(u32 section_size)
805 * Section size mapping:
806 * 0x0: 16-MiB section
807 * 0x1: 32-MiB section
808 * 0x2: 64-MiB section
809 * 0x3: 128-MiB section
810 * 0x4: 256-MiB section
811 * 0x5: 512-MiB section
815 section_size >>= 24; /* divide by 16 MB */
816 return log_2_n_round_down(section_size);
819 static void emif_calculate_regs(
820 const struct emif_device_details *emif_dev_details,
821 u32 freq, struct emif_regs *regs)
824 const struct lpddr2_addressing *addressing;
825 const struct lpddr2_ac_timings *timings;
826 const struct lpddr2_min_tck *min_tck;
827 const struct lpddr2_device_details *cs0_dev_details =
828 emif_dev_details->cs0_device_details;
829 const struct lpddr2_device_details *cs1_dev_details =
830 emif_dev_details->cs1_device_details;
831 const struct lpddr2_device_timings *cs0_dev_timings =
832 emif_dev_details->cs0_device_timings;
834 emif_assert(emif_dev_details);
837 * You can not have a device on CS1 without one on CS0
838 * So configuring EMIF without a device on CS0 doesn't
841 emif_assert(cs0_dev_details);
842 emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
844 * If there is a device on CS1 it should be same type as CS0
845 * (or NVM. But NVM is not supported in this driver yet)
847 emif_assert((cs1_dev_details == NULL) ||
848 (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
849 (cs0_dev_details->type == cs1_dev_details->type));
850 emif_assert(freq <= MAX_LPDDR2_FREQ);
852 set_ddr_clk_period(freq);
855 * The device on CS0 is used for all timing calculations
856 * There is only one set of registers for timings per EMIF. So, if the
857 * second CS(CS1) has a device, it should have the same timings as the
860 timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
861 emif_assert(timings);
862 min_tck = cs0_dev_timings->min_tck;
864 temp = addressing_table_index(cs0_dev_details->type,
865 cs0_dev_details->density,
866 cs0_dev_details->io_width);
868 emif_assert((temp >= 0));
869 addressing = &(addressing_table[temp]);
870 emif_assert(addressing);
872 sys_freq = get_sys_clk_freq();
874 regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
876 addressing, RL_BOOT);
878 regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
880 addressing, RL_FINAL);
882 regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
884 regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
886 regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
888 regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
890 regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
892 regs->temp_alert_config =
893 get_temp_alert_config(cs1_dev_details, addressing, 0);
895 regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
896 LPDDR2_VOLTAGE_STABLE);
898 regs->emif_ddr_phy_ctlr_1_init =
899 get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
901 regs->emif_ddr_phy_ctlr_1 =
902 get_ddr_phy_ctrl_1(freq, RL_FINAL);
906 print_timing_reg(regs->sdram_config_init);
907 print_timing_reg(regs->sdram_config);
908 print_timing_reg(regs->ref_ctrl);
909 print_timing_reg(regs->sdram_tim1);
910 print_timing_reg(regs->sdram_tim2);
911 print_timing_reg(regs->sdram_tim3);
912 print_timing_reg(regs->read_idle_ctrl);
913 print_timing_reg(regs->temp_alert_config);
914 print_timing_reg(regs->zq_config);
915 print_timing_reg(regs->emif_ddr_phy_ctlr_1);
916 print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
918 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
920 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
921 const char *get_lpddr2_type(u8 type_id)
933 const char *get_lpddr2_io_width(u8 width_id)
936 case LPDDR2_IO_WIDTH_8:
938 case LPDDR2_IO_WIDTH_16:
940 case LPDDR2_IO_WIDTH_32:
947 const char *get_lpddr2_manufacturer(u32 manufacturer)
949 switch (manufacturer) {
950 case LPDDR2_MANUFACTURER_SAMSUNG:
952 case LPDDR2_MANUFACTURER_QIMONDA:
954 case LPDDR2_MANUFACTURER_ELPIDA:
956 case LPDDR2_MANUFACTURER_ETRON:
958 case LPDDR2_MANUFACTURER_NANYA:
960 case LPDDR2_MANUFACTURER_HYNIX:
962 case LPDDR2_MANUFACTURER_MOSEL:
964 case LPDDR2_MANUFACTURER_WINBOND:
966 case LPDDR2_MANUFACTURER_ESMT:
968 case LPDDR2_MANUFACTURER_SPANSION:
970 case LPDDR2_MANUFACTURER_SST:
972 case LPDDR2_MANUFACTURER_ZMOS:
974 case LPDDR2_MANUFACTURER_INTEL:
976 case LPDDR2_MANUFACTURER_NUMONYX:
978 case LPDDR2_MANUFACTURER_MICRON:
985 static void display_sdram_details(u32 emif_nr, u32 cs,
986 struct lpddr2_device_details *device)
989 const char *type_str;
990 char density_str[10];
993 debug("EMIF%d CS%d\t", emif_nr, cs);
1000 mfg_str = get_lpddr2_manufacturer(device->manufacturer);
1001 type_str = get_lpddr2_type(device->type);
1003 density = lpddr2_density_2_size_in_mbytes[device->density];
1004 if ((density / 1024 * 1024) == density) {
1006 sprintf(density_str, "%d GB", density);
1008 sprintf(density_str, "%d MB", density);
1009 if (mfg_str && type_str)
1010 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
1013 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
1014 struct lpddr2_device_details *lpddr2_device)
1018 mr = get_mr(base, cs, LPDDR2_MR0);
1020 /* Mode register value bigger than 8 bit */
1024 temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
1029 temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
1032 /* DNV supported - But DNV is only supported for NVM */
1036 mr = get_mr(base, cs, LPDDR2_MR4);
1038 /* Mode register value bigger than 8 bit */
1042 mr = get_mr(base, cs, LPDDR2_MR5);
1044 /* Mode register value bigger than 8 bit */
1048 if (!get_lpddr2_manufacturer(mr)) {
1049 /* Manufacturer not identified */
1052 lpddr2_device->manufacturer = mr;
1054 mr = get_mr(base, cs, LPDDR2_MR6);
1056 /* Mode register value bigger than 8 bit */
1060 mr = get_mr(base, cs, LPDDR2_MR7);
1062 /* Mode register value bigger than 8 bit */
1066 mr = get_mr(base, cs, LPDDR2_MR8);
1068 /* Mode register value bigger than 8 bit */
1072 temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
1073 if (!get_lpddr2_type(temp)) {
1077 lpddr2_device->type = temp;
1079 temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
1080 if (temp > LPDDR2_DENSITY_32Gb) {
1081 /* Density not supported */
1084 lpddr2_device->density = temp;
1086 temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
1087 if (!get_lpddr2_io_width(temp)) {
1088 /* IO width unsupported value */
1091 lpddr2_device->io_width = temp;
1094 * If all the above tests pass we should
1095 * have a device on this chip-select
1100 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1101 struct lpddr2_device_details *lpddr2_dev_details)
1104 u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
1106 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1108 if (!lpddr2_dev_details)
1111 /* Do the minimum init for mode register accesses */
1112 if (!(running_from_sdram() || warm_reset())) {
1113 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
1114 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1117 if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1120 display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1122 return lpddr2_dev_details;
1124 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1126 static void do_sdram_init(u32 base)
1128 const struct emif_regs *regs;
1129 u32 in_sdram, emif_nr;
1131 debug(">>do_sdram_init() %x\n", base);
1133 in_sdram = running_from_sdram();
1134 emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1136 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1137 emif_get_reg_dump(emif_nr, ®s);
1139 debug("EMIF: reg dump not provided\n");
1144 * The user has not provided the register values. We need to
1145 * calculate it based on the timings and the DDR frequency
1147 struct emif_device_details dev_details;
1148 struct emif_regs calculated_regs;
1151 * Get device details:
1152 * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1153 * - Obtained from user otherwise
1155 struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1156 emif_reset_phy(base);
1157 dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1159 dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1161 emif_reset_phy(base);
1163 /* Return if no devices on this EMIF */
1164 if (!dev_details.cs0_device_details &&
1165 !dev_details.cs1_device_details) {
1170 * Get device timings:
1171 * - Default timings specified by JESD209-2 if
1172 * CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1173 * - Obtained from user otherwise
1175 emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1176 &dev_details.cs1_device_timings);
1178 /* Calculate the register values */
1179 emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1180 regs = &calculated_regs;
1181 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1184 * Initializing the DDR device can not happen from SDRAM.
1185 * Changing the timing registers in EMIF can happen(going from one
1188 if (!in_sdram && (!warm_reset() || is_dra7xx())) {
1189 if (emif_sdram_type(regs->sdram_config) ==
1190 EMIF_SDRAM_TYPE_LPDDR2)
1191 lpddr2_init(base, regs);
1192 #ifndef CONFIG_OMAP44XX
1194 ddr3_init(base, regs);
1197 #ifdef CONFIG_OMAP54X
1198 if (warm_reset() && (emif_sdram_type(regs->sdram_config) ==
1199 EMIF_SDRAM_TYPE_DDR3) && !is_dra7xx()) {
1200 set_lpmode_selfrefresh(base);
1201 emif_reset_phy(base);
1202 omap5_ddr3_leveling(base, regs);
1206 /* Write to the shadow registers */
1207 emif_update_timings(base, regs);
1209 debug("<<do_sdram_init() %x\n", base);
1212 void emif_post_init_config(u32 base)
1214 struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1215 u32 omap_rev = omap_revision();
1217 /* reset phy on ES2.0 */
1218 if (omap_rev == OMAP4430_ES2_0)
1219 emif_reset_phy(base);
1221 /* Put EMIF back in smart idle on ES1.0 */
1222 if (omap_rev == OMAP4430_ES1_0)
1223 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1226 void dmm_init(u32 base)
1228 const struct dmm_lisa_map_regs *lisa_map_regs;
1229 u32 i, section, valid;
1231 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1232 emif_get_dmm_regs(&lisa_map_regs);
1234 u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1235 u32 section_cnt, sys_addr;
1236 struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1240 sys_addr = CONFIG_SYS_SDRAM_BASE;
1241 emif1_size = get_emif_mem_size(EMIF1_BASE);
1242 emif2_size = get_emif_mem_size(EMIF2_BASE);
1243 debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1245 if (!emif1_size && !emif2_size)
1248 /* symmetric interleaved section */
1249 if (emif1_size && emif2_size) {
1250 mapped_size = min(emif1_size, emif2_size);
1251 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1252 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1254 section_map |= (sys_addr >> 24) <<
1255 EMIF_SYS_ADDR_SHIFT;
1256 section_map |= get_dmm_section_size_map(mapped_size * 2)
1257 << EMIF_SYS_SIZE_SHIFT;
1258 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1259 emif1_size -= mapped_size;
1260 emif2_size -= mapped_size;
1261 sys_addr += (mapped_size * 2);
1266 * Single EMIF section(we can have a maximum of 1 single EMIF
1267 * section- either EMIF1 or EMIF2 or none, but not both)
1270 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1271 section_map |= get_dmm_section_size_map(emif1_size)
1272 << EMIF_SYS_SIZE_SHIFT;
1274 section_map |= (mapped_size >> 24) <<
1275 EMIF_SDRC_ADDR_SHIFT;
1277 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1281 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1282 section_map |= get_dmm_section_size_map(emif2_size) <<
1283 EMIF_SYS_SIZE_SHIFT;
1285 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1287 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1291 if (section_cnt == 2) {
1292 /* Only 1 section - either symmetric or single EMIF */
1293 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1294 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1295 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1297 /* 2 sections - 1 symmetric, 1 single EMIF */
1298 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1299 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1302 /* TRAP for invalid TILER mappings in section 0 */
1303 lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1305 if (omap_revision() >= OMAP4460_ES1_0)
1306 lis_map_regs_calculated.is_ma_present = 1;
1308 lisa_map_regs = &lis_map_regs_calculated;
1310 struct dmm_lisa_map_regs *hw_lisa_map_regs =
1311 (struct dmm_lisa_map_regs *)base;
1313 writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1314 writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1315 writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1316 writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1318 writel(lisa_map_regs->dmm_lisa_map_3,
1319 &hw_lisa_map_regs->dmm_lisa_map_3);
1320 writel(lisa_map_regs->dmm_lisa_map_2,
1321 &hw_lisa_map_regs->dmm_lisa_map_2);
1322 writel(lisa_map_regs->dmm_lisa_map_1,
1323 &hw_lisa_map_regs->dmm_lisa_map_1);
1324 writel(lisa_map_regs->dmm_lisa_map_0,
1325 &hw_lisa_map_regs->dmm_lisa_map_0);
1327 if (lisa_map_regs->is_ma_present) {
1329 (struct dmm_lisa_map_regs *)MA_BASE;
1331 writel(lisa_map_regs->dmm_lisa_map_3,
1332 &hw_lisa_map_regs->dmm_lisa_map_3);
1333 writel(lisa_map_regs->dmm_lisa_map_2,
1334 &hw_lisa_map_regs->dmm_lisa_map_2);
1335 writel(lisa_map_regs->dmm_lisa_map_1,
1336 &hw_lisa_map_regs->dmm_lisa_map_1);
1337 writel(lisa_map_regs->dmm_lisa_map_0,
1338 &hw_lisa_map_regs->dmm_lisa_map_0);
1340 setbits_le32(MA_PRIORITY, MA_HIMEM_INTERLEAVE_UN_MASK);
1344 * EMIF should be configured only when
1345 * memory is mapped on it. Using emif1_enabled
1346 * and emif2_enabled variables for this.
1350 for (i = 0; i < 4; i++) {
1351 section = __raw_readl(DMM_BASE + i*4);
1352 valid = (section & EMIF_SDRC_MAP_MASK) >>
1353 (EMIF_SDRC_MAP_SHIFT);
1368 static void do_bug0039_workaround(u32 base)
1370 u32 val, i, clkctrl;
1371 struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
1372 const struct read_write_regs *bug_00339_regs;
1374 u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
1375 u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
1380 bug_00339_regs = get_bug_regs(&iterations);
1382 /* Put EMIF in to idle */
1383 clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
1384 __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
1386 /* Copy the phy status registers in to phy ctrl shadow registers */
1387 for (i = 0; i < iterations; i++) {
1388 val = __raw_readl(phy_status_base +
1389 bug_00339_regs[i].read_reg - 1);
1391 __raw_writel(val, phy_ctrl_base +
1392 ((bug_00339_regs[i].write_reg - 1) << 1));
1394 __raw_writel(val, phy_ctrl_base +
1395 (bug_00339_regs[i].write_reg << 1) - 1);
1398 /* Disable leveling */
1399 writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
1401 __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl);
1405 * SDRAM initialization:
1406 * SDRAM initialization has two parts:
1407 * 1. Configuring the SDRAM device
1408 * 2. Update the AC timings related parameters in the EMIF module
1409 * (1) should be done only once and should not be done while we are
1410 * running from SDRAM.
1411 * (2) can and should be done more than once if OPP changes.
1412 * Particularly, this may be needed when we boot without SPL and
1413 * and using Configuration Header(CH). ROM code supports only at 50% OPP
1414 * at boot (low power boot). So u-boot has to switch to OPP100 and update
1415 * the frequency. So,
1416 * Doing (1) and (2) makes sense - first time initialization
1417 * Doing (2) and not (1) makes sense - OPP change (when using CH)
1418 * Doing (1) and not (2) doen't make sense
1419 * See do_sdram_init() for the details
1421 void sdram_init(void)
1423 u32 in_sdram, size_prog, size_detect;
1424 struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
1425 u32 sdram_type = emif_sdram_type(emif->emif_sdram_config);
1427 debug(">>sdram_init()\n");
1429 if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1432 in_sdram = running_from_sdram();
1433 debug("in_sdram = %d\n", in_sdram);
1436 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1437 bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1438 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1439 writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1446 do_sdram_init(EMIF1_BASE);
1449 do_sdram_init(EMIF2_BASE);
1451 if (!(in_sdram || warm_reset())) {
1453 emif_post_init_config(EMIF1_BASE);
1455 emif_post_init_config(EMIF2_BASE);
1458 /* for the shadow registers to take effect */
1459 if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1462 /* Do some testing after the init */
1464 size_prog = omap_sdram_size();
1465 size_prog = log_2_n_round_down(size_prog);
1466 size_prog = (1 << size_prog);
1468 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1470 /* Compare with the size programmed */
1471 if (size_detect != size_prog) {
1472 printf("SDRAM: identified size not same as expected"
1473 " size identified: %x expected: %x\n",
1477 debug("get_ram_size() successful");
1480 if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
1481 (!in_sdram && !warm_reset()) && (!is_dra7xx())) {
1483 do_bug0039_workaround(EMIF1_BASE);
1485 do_bug0039_workaround(EMIF2_BASE);
1488 debug("<<sdram_init()\n");