2 * TI SATA platform driver
5 * Texas Instruments, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/clock.h>
14 #include <asm/arch/sata.h>
16 #include "pipe3-phy.h"
18 static struct pipe3_dpll_map dpll_map_sata[] = {
19 {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */
20 {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
21 {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
22 {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */
23 {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */
24 {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
28 struct omap_pipe3 sata_phy = {
29 .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
30 /* .power_reg is updated at runtime */
31 .dpll_map = dpll_map_sata,
34 int omap_sata_init(void)
39 u32 const clk_domains_sata[] = {
43 u32 const clk_modules_hw_auto_sata[] = {
44 (*prcm)->cm_l3init_ocp2scp3_clkctrl,
48 u32 const clk_modules_explicit_en_sata[] = {
49 (*prcm)->cm_l3init_sata_clkctrl,
53 do_enable_clocks(clk_domains_sata,
54 clk_modules_hw_auto_sata,
55 clk_modules_explicit_en_sata,
58 /* Enable optional functional clock for SATA */
59 setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
60 SATA_CLKCTRL_OPTFCLKEN_MASK);
62 sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
64 /* Power up the PHY */
65 phy_pipe3_power_on(&sata_phy);
67 /* Enable SATA module, No Idle, No Standby */
68 val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
69 writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
71 ret = ahci_init(DWC_AHSATA_BASE);