3 * Common board functions for OMAP3 based boards.
5 * (C) Copyright 2004-2008
6 * Texas Instruments, <www.ti.com>
9 * Sunil Kumar <sunilsaini05@gmail.com>
10 * Shashi Ranjan <shashiranjanmca05@gmail.com>
12 * Derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com>
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/arch/sys_proto.h>
38 #include <asm/arch/mem.h>
39 #include <asm/cache.h>
40 #include <asm/armv7.h>
41 #include <asm/arch/gpio.h>
43 #include <asm/omap_common.h>
44 #include <asm/arch/mmc_host_def.h>
46 #include <linux/compiler.h>
49 extern omap3_sysinfo sysinfo;
50 static void omap3_setup_aux_cr(void);
51 static void omap3_invalidate_l2_cache_secure(void);
53 static const struct gpio_bank gpio_bank_34xx[6] = {
54 { (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
55 { (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
56 { (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
57 { (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
58 { (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
59 { (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
62 const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
64 #ifdef CONFIG_SPL_BUILD
66 * We use static variables because global data is not ready yet.
67 * Initialized data is available in SPL right from the beginning.
68 * We would not typically need to save these parameters in regular
69 * U-Boot. This is needed only in SPL at the moment.
71 u32 omap3_boot_device = BOOT_DEVICE_NAND;
73 /* auto boot mode detection is not possible for OMAP3 - hard code */
74 u32 spl_boot_mode(void)
76 switch (spl_boot_device()) {
77 case BOOT_DEVICE_MMC2:
78 return MMCSD_MODE_RAW;
79 case BOOT_DEVICE_MMC1:
80 return MMCSD_MODE_FAT;
83 puts("spl: ERROR: unknown device - can't select boot mode\n");
88 u32 spl_boot_device(void)
90 return omap3_boot_device;
93 int board_mmc_init(bd_t *bis)
95 switch (spl_boot_device()) {
96 case BOOT_DEVICE_MMC1:
97 omap_mmc_init(0, 0, 0);
99 case BOOT_DEVICE_MMC2:
100 case BOOT_DEVICE_MMC2_2:
101 omap_mmc_init(1, 0, 0);
107 void spl_board_init(void)
109 #ifdef CONFIG_SPL_I2C_SUPPORT
110 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
113 #endif /* CONFIG_SPL_BUILD */
116 /******************************************************************************
117 * Routine: secure_unlock
118 * Description: Setup security registers for access
120 *****************************************************************************/
121 void secure_unlock_mem(void)
123 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
124 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
125 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
126 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
127 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
129 /* Protection Module Register Target APE (PM_RT) */
130 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
131 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
132 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
133 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
135 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
136 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
137 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
139 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
140 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
141 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
142 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
145 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
146 writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
147 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
149 /* SDRC region 0 public */
150 writel(UNLOCK_1, &sms_base->rg_att0);
153 /******************************************************************************
154 * Routine: secureworld_exit()
155 * Description: If chip is EMU and boot type is external
156 * configure secure registers and exit secure world
158 *****************************************************************************/
159 void secureworld_exit()
163 /* configure non-secure access control register */
164 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
165 /* enabling co-processor CP10 and CP11 accesses in NS world */
166 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
168 * allow allocation of locked TLBs and L2 lines in NS world
169 * allow use of PLE registers in NS world also
171 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
172 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
174 /* Enable ASA in ACR register */
175 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
176 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
177 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
179 /* Exiting secure world */
180 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
181 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
182 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
185 /******************************************************************************
186 * Routine: try_unlock_sram()
187 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
189 *****************************************************************************/
190 void try_unlock_memory()
193 int in_sdram = is_running_in_sdram();
196 * if GP device unlock device SRAM for general use
197 * secure code breaks for Secure/Emulation device - HS/E/T
199 mode = get_device_type();
200 if (mode == GP_DEVICE)
204 * If device is EMU and boot is XIP external booting
205 * Unlock firewalls and disable L2 and put chip
206 * out of secure world
208 * Assuming memories are unlocked by the demon who put us in SDRAM
210 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
219 /******************************************************************************
221 * Description: Does early system init of muxing and clocks.
222 * - Called path is with SRAM stack.
223 *****************************************************************************/
226 int in_sdram = is_running_in_sdram();
232 /* Errata workarounds */
233 omap3_setup_aux_cr();
235 #ifndef CONFIG_SYS_L2CACHE_OFF
236 /* Invalidate L2-cache from secure mode */
237 omap3_invalidate_l2_cache_secure();
247 #ifdef CONFIG_USB_EHCI_OMAP
248 ehci_clocks_enable();
251 #ifdef CONFIG_SPL_BUILD
252 preloader_console_init();
262 * Routine: misc_init_r
263 * Description: A basic misc_init_r that just displays the die ID
265 int __weak misc_init_r(void)
272 /******************************************************************************
273 * Routine: wait_for_command_complete
274 * Description: Wait for posting to finish on watchdog
275 *****************************************************************************/
276 void wait_for_command_complete(struct watchdog *wd_base)
280 pending = readl(&wd_base->wwps);
284 /******************************************************************************
285 * Routine: watchdog_init
286 * Description: Shut down watch dogs
287 *****************************************************************************/
288 void watchdog_init(void)
290 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
291 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
294 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
295 * either taken care of by ROM (HS/EMU) or not accessible (GP).
296 * We need to take care of WD2-MPU or take a PRCM reset. WD3
297 * should not be running and does not generate a PRCM reset.
300 sr32(&prcm_base->fclken_wkup, 5, 1, 1);
301 sr32(&prcm_base->iclken_wkup, 5, 1, 1);
302 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
304 writel(WD_UNLOCK1, &wd2_base->wspr);
305 wait_for_command_complete(wd2_base);
306 writel(WD_UNLOCK2, &wd2_base->wspr);
309 /******************************************************************************
310 * Dummy function to handle errors for EABI incompatibility
311 *****************************************************************************/
316 #if defined(CONFIG_NAND_OMAP_GPMC) & !defined(CONFIG_SPL_BUILD)
317 /******************************************************************************
318 * OMAP3 specific command to switch between NAND HW and SW ecc
319 *****************************************************************************/
320 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
324 if (strncmp(argv[1], "hw", 2) == 0)
325 omap_nand_switch_ecc(1);
326 else if (strncmp(argv[1], "sw", 2) == 0)
327 omap_nand_switch_ecc(0);
334 printf ("Usage: nandecc %s\n", cmdtp->usage);
339 nandecc, 2, 1, do_switch_ecc,
340 "switch OMAP3 NAND ECC calculation algorithm",
341 "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
344 #endif /* CONFIG_NAND_OMAP_GPMC & !CONFIG_SPL_BUILD */
346 #ifdef CONFIG_DISPLAY_BOARDINFO
348 * Print board information
350 int checkboard (void)
359 printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
360 sysinfo.nand_string);
364 #endif /* CONFIG_DISPLAY_BOARDINFO */
366 static void omap3_emu_romcode_call(u32 service_id, u32 *parameters)
368 u32 i, num_params = *parameters;
369 u32 *sram_scratch_space = (u32 *)OMAP3_PUBLIC_SRAM_SCRATCH_AREA;
372 * copy the parameters to an un-cached area to avoid coherency
375 for (i = 0; i < num_params; i++) {
376 __raw_writel(*parameters, sram_scratch_space);
378 sram_scratch_space++;
381 /* Now make the PPA call */
382 do_omap3_emu_romcode_call(service_id, OMAP3_PUBLIC_SRAM_SCRATCH_AREA);
385 static void omap3_update_aux_cr_secure(u32 set_bits, u32 clear_bits)
390 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
394 if (get_device_type() == GP_DEVICE) {
395 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_WRITE_ACR,
398 struct emu_hal_params emu_romcode_params;
399 emu_romcode_params.num_params = 1;
400 emu_romcode_params.param1 = acr;
401 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_WRITE_ACR,
402 (u32 *)&emu_romcode_params);
406 static void omap3_update_aux_cr(u32 set_bits, u32 clear_bits)
411 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
415 /* Write ACR - affects non-secure banked bits */
416 asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (acr));
419 static void omap3_setup_aux_cr(void)
421 /* Workaround for Cortex-A8 errata: #454179 #430973
423 * Set "Disable Branch Size Mispredicts" bit
424 * Workaround for erratum #621766
426 * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
428 omap3_update_aux_cr_secure(0xE0, 0);
431 #ifndef CONFIG_SYS_L2CACHE_OFF
432 /* Invalidate the entire L2 cache from secure mode */
433 static void omap3_invalidate_l2_cache_secure(void)
435 if (get_device_type() == GP_DEVICE) {
436 omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL,
439 struct emu_hal_params emu_romcode_params;
440 emu_romcode_params.num_params = 1;
441 emu_romcode_params.param1 = 0;
442 omap3_emu_romcode_call(OMAP3_EMU_HAL_API_L2_INVAL,
443 (u32 *)&emu_romcode_params);
447 void v7_outer_cache_enable(void)
450 omap3_update_aux_cr_secure(0x2, 0);
453 * On some revisions L2EN bit is banked on some revisions it's not
454 * No harm in setting both banked bits(in fact this is required
457 omap3_update_aux_cr(0x2, 0);
460 void omap3_outer_cache_disable(void)
463 omap3_update_aux_cr_secure(0, 0x2);
466 * On some revisions L2EN bit is banked on some revisions it's not
467 * No harm in clearing both banked bits(in fact this is required
470 omap3_update_aux_cr(0, 0x2);
474 #ifndef CONFIG_SYS_DCACHE_OFF
475 void enable_caches(void)
477 /* Enable D-cache. I-cache is already enabled in start.S */