3 * Common board functions for OMAP3 based boards.
5 * (C) Copyright 2004-2008
6 * Texas Instruments, <www.ti.com>
9 * Sunil Kumar <sunilsaini05@gmail.com>
10 * Shashi Ranjan <shashiranjanmca05@gmail.com>
12 * Derived from Beagle Board and 3430 SDP code by
13 * Richard Woodruff <r-woodruff2@ti.com>
14 * Syed Mohammed Khasim <khasim@ti.com>
17 * See file CREDITS for list of people who contributed to this
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
37 #include <asm/arch/sys_proto.h>
38 #include <asm/arch/mem.h>
39 #include <asm/cache.h>
41 extern omap3_sysinfo sysinfo;
43 /******************************************************************************
45 * Description: spinning delay to use before udelay works
46 *****************************************************************************/
47 static inline void delay(unsigned long loops)
49 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
50 "bne 1b":"=r" (loops):"0"(loops));
53 /******************************************************************************
54 * Routine: secure_unlock
55 * Description: Setup security registers for access
57 *****************************************************************************/
58 void secure_unlock_mem(void)
60 struct pm *pm_rt_ape_base = (struct pm *)PM_RT_APE_BASE_ADDR_ARM;
61 struct pm *pm_gpmc_base = (struct pm *)PM_GPMC_BASE_ADDR_ARM;
62 struct pm *pm_ocm_ram_base = (struct pm *)PM_OCM_RAM_BASE_ADDR_ARM;
63 struct pm *pm_iva2_base = (struct pm *)PM_IVA2_BASE_ADDR_ARM;
64 struct sms *sms_base = (struct sms *)OMAP34XX_SMS_BASE;
66 /* Protection Module Register Target APE (PM_RT) */
67 writel(UNLOCK_1, &pm_rt_ape_base->req_info_permission_1);
68 writel(UNLOCK_1, &pm_rt_ape_base->read_permission_0);
69 writel(UNLOCK_1, &pm_rt_ape_base->wirte_permission_0);
70 writel(UNLOCK_2, &pm_rt_ape_base->addr_match_1);
72 writel(UNLOCK_3, &pm_gpmc_base->req_info_permission_0);
73 writel(UNLOCK_3, &pm_gpmc_base->read_permission_0);
74 writel(UNLOCK_3, &pm_gpmc_base->wirte_permission_0);
76 writel(UNLOCK_3, &pm_ocm_ram_base->req_info_permission_0);
77 writel(UNLOCK_3, &pm_ocm_ram_base->read_permission_0);
78 writel(UNLOCK_3, &pm_ocm_ram_base->wirte_permission_0);
79 writel(UNLOCK_2, &pm_ocm_ram_base->addr_match_2);
82 writel(UNLOCK_3, &pm_iva2_base->req_info_permission_0);
83 writel(UNLOCK_3, &pm_iva2_base->read_permission_0);
84 writel(UNLOCK_3, &pm_iva2_base->wirte_permission_0);
86 /* SDRC region 0 public */
87 writel(UNLOCK_1, &sms_base->rg_att0);
90 /******************************************************************************
91 * Routine: secureworld_exit()
92 * Description: If chip is EMU and boot type is external
93 * configure secure registers and exit secure world
95 *****************************************************************************/
96 void secureworld_exit()
100 /* configrue non-secure access control register */
101 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
102 /* enabling co-processor CP10 and CP11 accesses in NS world */
103 __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
105 * allow allocation of locked TLBs and L2 lines in NS world
106 * allow use of PLE registers in NS world also
108 __asm__ __volatile__("orr %0, %0, #0x70000":"=r"(i));
109 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 2":"=r"(i));
111 /* Enable ASA in ACR register */
112 __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
113 __asm__ __volatile__("orr %0, %0, #0x10":"=r"(i));
114 __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
116 /* Exiting secure world */
117 __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 0":"=r"(i));
118 __asm__ __volatile__("orr %0, %0, #0x31":"=r"(i));
119 __asm__ __volatile__("mcr p15, 0, %0, c1, c1, 0":"=r"(i));
122 /******************************************************************************
123 * Routine: setup_auxcr()
124 * Description: Write to AuxCR desired value using SMI.
126 *****************************************************************************/
130 volatile unsigned int j;
131 /* Save r0, r12 and restore them after usage */
132 __asm__ __volatile__("mov %0, r12":"=r"(j));
133 __asm__ __volatile__("mov %0, r0":"=r"(i));
136 * GP Device ROM code API usage here
137 * r12 = AUXCR Write function and r0 value
139 __asm__ __volatile__("mov r12, #0x3");
140 __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
142 __asm__ __volatile__("orr r0, r0, #0x10");
144 __asm__ __volatile__("orr r0, r0, #1 << 5");
145 /* SMI instruction to call ROM Code API */
146 __asm__ __volatile__(".word 0xE1600070");
147 /* Set PLD_FWD bit in L2AUXCR (Cortex-A8 erratum 725233 workaround) */
148 __asm__ __volatile__("mov r12, #0x2");
149 __asm__ __volatile__("mrc p15, 1, r0, c9, c0, 2");
150 __asm__ __volatile__("orr r0, r0, #1 << 27");
151 /* SMI instruction to call ROM Code API */
152 __asm__ __volatile__(".word 0xE1600070");
153 __asm__ __volatile__("mov r0, %0":"=r"(i));
154 __asm__ __volatile__("mov r12, %0":"=r"(j));
157 /******************************************************************************
158 * Routine: try_unlock_sram()
159 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
161 *****************************************************************************/
162 void try_unlock_memory()
165 int in_sdram = is_running_in_sdram();
168 * if GP device unlock device SRAM for general use
169 * secure code breaks for Secure/Emulation device - HS/E/T
171 mode = get_device_type();
172 if (mode == GP_DEVICE)
176 * If device is EMU and boot is XIP external booting
177 * Unlock firewalls and disable L2 and put chip
178 * out of secure world
180 * Assuming memories are unlocked by the demon who put us in SDRAM
182 if ((mode <= EMU_DEVICE) && (get_boot_type() == 0x1F)
191 /******************************************************************************
193 * Description: Does early system init of muxing and clocks.
194 * - Called path is with SRAM stack.
195 *****************************************************************************/
198 int in_sdram = is_running_in_sdram();
205 * Right now flushing at low MPU speed.
206 * Need to move after clock init
208 invalidate_dcache(get_device_type());
209 #ifndef CONFIG_ICACHE_OFF
219 * Writing to AuxCR in U-boot using SMI for GP DEV
220 * Currently SMI in Kernel on ES2 devices seems to have an issue
221 * Once that is resolved, we can postpone this config to kernel
223 if (get_device_type() == GP_DEVICE)
237 /******************************************************************************
238 * Routine: wait_for_command_complete
239 * Description: Wait for posting to finish on watchdog
240 *****************************************************************************/
241 void wait_for_command_complete(struct watchdog *wd_base)
245 pending = readl(&wd_base->wwps);
249 /******************************************************************************
250 * Routine: watchdog_init
251 * Description: Shut down watch dogs
252 *****************************************************************************/
253 void watchdog_init(void)
255 struct watchdog *wd2_base = (struct watchdog *)WD2_BASE;
256 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
259 * There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
260 * either taken care of by ROM (HS/EMU) or not accessible (GP).
261 * We need to take care of WD2-MPU or take a PRCM reset. WD3
262 * should not be running and does not generate a PRCM reset.
265 sr32(&prcm_base->fclken_wkup, 5, 1, 1);
266 sr32(&prcm_base->iclken_wkup, 5, 1, 1);
267 wait_on_value(ST_WDT2, 0x20, &prcm_base->idlest_wkup, 5);
269 writel(WD_UNLOCK1, &wd2_base->wspr);
270 wait_for_command_complete(wd2_base);
271 writel(WD_UNLOCK2, &wd2_base->wspr);
274 /******************************************************************************
275 * Dummy function to handle errors for EABI incompatibility
276 *****************************************************************************/
281 #ifdef CONFIG_NAND_OMAP_GPMC
282 /******************************************************************************
283 * OMAP3 specific command to switch between NAND HW and SW ecc
284 *****************************************************************************/
285 static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
289 if (strncmp(argv[1], "hw", 2) == 0)
290 omap_nand_switch_ecc(1);
291 else if (strncmp(argv[1], "sw", 2) == 0)
292 omap_nand_switch_ecc(0);
299 printf ("Usage: nandecc %s\n", cmdtp->usage);
304 nandecc, 2, 1, do_switch_ecc,
305 "switch OMAP3 NAND ECC calculation algorithm",
306 "[hw/sw] - Switch between NAND hardware (hw) or software (sw) ecc algorithm"
309 #endif /* CONFIG_NAND_OMAP_GPMC */
311 #ifdef CONFIG_DISPLAY_BOARDINFO
313 * Print board information
315 int checkboard (void)
324 printf("%s + %s/%s\n", sysinfo.board_string, mem_s,
325 sysinfo.nand_string);
329 #endif /* CONFIG_DISPLAY_BOARDINFO */