3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
8 * Derived from Beagle Board and OMAP3 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/clock.h>
18 #include <asm/arch/clocks_omap3.h>
19 #include <asm/arch/mem.h>
20 #include <asm/arch/sys_proto.h>
21 #include <environment.h>
24 /******************************************************************************
25 * get_sys_clk_speed() - determine reference oscillator speed
26 * based on known 32kHz clock and gptimer.
27 *****************************************************************************/
28 u32 get_osc_clk_speed(void)
30 u32 start, cstart, cend, cdiff, cdiv, val;
31 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
32 struct prm *prm_base = (struct prm *)PRM_BASE;
33 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
34 struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
36 val = readl(&prm_base->clksrc_ctrl);
38 if (val & SYSCLKDIV_2)
44 val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
46 /* select sys_clk for GPT1 */
47 writel(val, &prcm_base->clksel_wkup);
49 /* Enable I and F Clocks for GPT1 */
50 val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
51 writel(val, &prcm_base->iclken_wkup);
53 val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
54 writel(val, &prcm_base->fclken_wkup);
56 writel(0, &gpt1_base->tldr); /* start counting at 0 */
57 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
59 /* enable 32kHz source, determine sys_clk via gauging */
61 /* start time in 20 cycles */
62 start = 20 + readl(&s32k_base->s32k_cr);
64 /* dead loop till start time */
65 while (readl(&s32k_base->s32k_cr) < start);
67 /* get start sys_clk count */
68 cstart = readl(&gpt1_base->tcrr);
70 /* wait for 40 cycles */
71 while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
72 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
73 cdiff = cend - cstart; /* get elapsed ticks */
76 /* based on number of ticks assign speed */
79 else if (cdiff > 15200)
81 else if (cdiff > 13000)
83 else if (cdiff > 9000)
85 else if (cdiff > 7600)
91 /******************************************************************************
92 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
93 * input oscillator clock frequency.
94 *****************************************************************************/
95 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
117 * OMAP34XX/35XX specific functions
120 static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
122 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
123 dpll_param *ptr = (dpll_param *) get_core_dpll_param();
124 void (*f_lock_pll) (u32, u32, u32, u32);
125 int xip_safe, p0, p1, p2, p3;
127 xip_safe = is_running_in_sram();
129 /* Moving to the right sysclk and ES rev base */
130 ptr = ptr + (3 * clk_index) + sil_index;
135 * sr32(CM_CLKSEL2_EMU) set override to work when asleep
137 sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
138 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
142 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
143 * work. write another value and then default value.
146 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
147 sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
148 sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
150 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
151 sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
153 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
154 sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
156 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
157 sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
159 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
160 sr32(&prcm_base->clksel1_pll, 6, 1, 0);
163 sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
165 sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
167 sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
169 sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
171 sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
173 sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
174 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
175 sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
177 sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
179 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
181 } else if (is_running_in_flash()) {
183 * if running from flash, jump to small relocated code
186 f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
189 p0 = readl(&prcm_base->clken_pll);
190 sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
191 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
192 sr32(&p0, 4, 4, ptr->fsel);
194 p1 = readl(&prcm_base->clksel1_pll);
195 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
196 sr32(&p1, 27, 5, ptr->m2);
197 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
198 sr32(&p1, 16, 11, ptr->m);
199 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
200 sr32(&p1, 8, 7, ptr->n);
201 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
204 p2 = readl(&prcm_base->clksel_core);
206 sr32(&p2, 8, 4, CORE_SSI_DIV);
208 sr32(&p2, 4, 2, CORE_FUSB_DIV);
210 sr32(&p2, 2, 2, CORE_L4_DIV);
212 sr32(&p2, 0, 2, CORE_L3_DIV);
214 p3 = (u32)&prcm_base->idlest_ckgen;
216 (*f_lock_pll) (p0, p1, p2, p3);
220 static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
222 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
223 dpll_param *ptr = (dpll_param *) get_per_dpll_param();
225 /* Moving it to the right sysclk base */
226 ptr = ptr + clk_index;
228 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
229 sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
230 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
233 * Errata 1.50 Workaround for OMAP3 ES1.0 only
234 * If using default divisors, write default divisor + 1
235 * and then the actual divisor value
238 sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1));
239 sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2);
241 sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1));
242 sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2);
244 sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1));
245 sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2);
247 sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1));
248 sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2);
249 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
250 sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1));
251 sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
254 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
255 sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m);
257 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
258 sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
260 /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
261 sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel);
263 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
264 sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
265 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
268 static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
270 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
271 dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
273 /* Moving it to the right sysclk base */
274 ptr = ptr + clk_index;
276 /* PER2 DPLL (DPLL5) */
277 sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
278 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
279 sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
280 sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
281 sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
282 sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); /* FREQSEL */
283 sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
284 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
287 static void mpu_init_34xx(u32 sil_index, u32 clk_index)
289 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
290 dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
292 /* Moving to the right sysclk and ES rev base */
293 ptr = ptr + (3 * clk_index) + sil_index;
295 /* MPU DPLL (unlocked already) */
297 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
298 sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
300 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
301 sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
303 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
304 sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
306 /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
307 sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel);
310 static void iva_init_34xx(u32 sil_index, u32 clk_index)
312 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
313 dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
315 /* Moving to the right sysclk and ES rev base */
316 ptr = ptr + (3 * clk_index) + sil_index;
319 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
320 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
321 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
323 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
324 sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
326 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
327 sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
329 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
330 sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
332 /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
333 sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel);
335 /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
336 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
338 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
342 * OMAP3630 specific functions
345 static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
347 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
348 dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
349 void (*f_lock_pll) (u32, u32, u32, u32);
350 int xip_safe, p0, p1, p2, p3;
352 xip_safe = is_running_in_sram();
354 /* Moving it to the right sysclk base */
360 /* Select relock bypass: CM_CLKEN_PLL[0:2] */
361 sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
362 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
365 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
366 sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
368 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
369 sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
371 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
372 sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
374 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
375 sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
377 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
378 sr32(&prcm_base->clksel1_pll, 6, 1, 0);
381 sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
383 sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
385 sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
387 sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
389 sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X);
391 sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
392 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
393 sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
395 sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
397 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
399 } else if (is_running_in_flash()) {
401 * if running from flash, jump to small relocated code
404 f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
407 p0 = readl(&prcm_base->clken_pll);
408 sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
409 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
410 sr32(&p0, 4, 4, ptr->fsel);
412 p1 = readl(&prcm_base->clksel1_pll);
413 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
414 sr32(&p1, 27, 5, ptr->m2);
415 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
416 sr32(&p1, 16, 11, ptr->m);
417 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
418 sr32(&p1, 8, 7, ptr->n);
419 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
422 p2 = readl(&prcm_base->clksel_core);
424 sr32(&p2, 8, 4, CORE_SSI_DIV);
426 sr32(&p2, 4, 2, CORE_FUSB_DIV);
428 sr32(&p2, 2, 2, CORE_L4_DIV);
430 sr32(&p2, 0, 2, CORE_L3_DIV);
432 p3 = (u32)&prcm_base->idlest_ckgen;
434 (*f_lock_pll) (p0, p1, p2, p3);
438 static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
440 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
441 struct dpll_per_36x_param *ptr;
443 ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
445 /* Moving it to the right sysclk base */
448 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
449 sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
450 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
452 /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
453 sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);
455 /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
456 sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);
458 /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
459 sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);
461 /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
462 sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);
464 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
465 sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
467 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
468 sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);
470 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
471 sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
473 /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
474 sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);
476 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
477 sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
478 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
481 static void mpu_init_36xx(u32 sil_index, u32 clk_index)
483 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
484 dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
486 /* Moving to the right sysclk */
489 /* MPU DPLL (unlocked already */
491 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
492 sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
494 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
495 sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
497 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
498 sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
501 static void iva_init_36xx(u32 sil_index, u32 clk_index)
503 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
504 dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
506 /* Moving to the right sysclk */
510 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
511 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
512 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
514 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
515 sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
517 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
518 sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
520 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
521 sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
523 /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
524 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
526 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
529 /******************************************************************************
530 * prcm_init() - inits clocks for PRCM as defined in clocks.h
531 * called from SRAM, or Flash (using temp SRAM stack).
532 *****************************************************************************/
535 u32 osc_clk = 0, sys_clkin_sel;
536 u32 clk_index, sil_index = 0;
537 struct prm *prm_base = (struct prm *)PRM_BASE;
538 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
541 * Gauge the input clock speed and find out the sys_clkin_sel
542 * value corresponding to the input clock.
544 osc_clk = get_osc_clk_speed();
545 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
547 /* set input crystal speed */
548 sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
550 /* If the input clock is greater than 19.2M always divide/2 */
551 if (sys_clkin_sel > 2) {
552 /* input clock divider */
553 sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
554 clk_index = sys_clkin_sel / 2;
556 /* input clock divider */
557 sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
558 clk_index = sys_clkin_sel;
561 if (get_cpu_family() == CPU_OMAP36XX) {
563 * In warm reset conditions on OMAP36xx/AM/DM37xx
564 * the rom code incorrectly sets the DPLL4 clock
565 * input divider to /6.5. Section 3.5.3.3.3.2.1 of
566 * the AM/DM37x TRM explains that the /6.5 divider
567 * is used only when the input clock is 13MHz.
569 * If the part is in this cpu family *and* the input
570 * clock *is not* 13 MHz, then reset the DPLL4 clock
571 * input divider to /1 as it should never set to /6.5
574 if (sys_clkin_sel != 1) /* 13 MHz */
575 /* Bit 8: DPLL4_CLKINP_DIV */
576 sr32(&prm_base->clksrc_ctrl, 8, 1, 0);
578 /* Unlock MPU DPLL (slows things down, and needed later) */
579 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
580 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
583 dpll3_init_36xx(0, clk_index);
584 dpll4_init_36xx(0, clk_index);
585 dpll5_init_34xx(0, clk_index);
586 iva_init_36xx(0, clk_index);
587 mpu_init_36xx(0, clk_index);
589 /* Lock MPU DPLL to set frequency */
590 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
591 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
595 * The DPLL tables are defined according to sysclk value and
596 * silicon revision. The clk_index value will be used to get
597 * the values for that input sysclk from the DPLL param table
598 * and sil_index will get the values for that SysClk for the
599 * appropriate silicon rev.
601 if (((get_cpu_family() == CPU_OMAP34XX)
602 && (get_cpu_rev() >= CPU_3XX_ES20)) ||
603 (get_cpu_family() == CPU_AM35XX))
606 /* Unlock MPU DPLL (slows things down, and needed later) */
607 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
608 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
611 dpll3_init_34xx(sil_index, clk_index);
612 dpll4_init_34xx(sil_index, clk_index);
613 dpll5_init_34xx(sil_index, clk_index);
614 if (get_cpu_family() != CPU_AM35XX)
615 iva_init_34xx(sil_index, clk_index);
617 mpu_init_34xx(sil_index, clk_index);
619 /* Lock MPU DPLL to set frequency */
620 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
621 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
625 /* Set up GPTimers to sys_clk source only */
626 sr32(&prcm_base->clksel_per, 0, 8, 0xff);
627 sr32(&prcm_base->clksel_wkup, 0, 1, 1);
633 * Enable usb ehci uhh, tll clocks
635 void ehci_clocks_enable(void)
637 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
639 /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
640 sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
642 * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
643 * and USBHOST_120M_FCLK (USBHOST_FCLK2)
645 sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
646 /* Enable USBTTL_ICLK */
647 sr32(&prcm_base->iclken3_core, 2, 1, 1);
648 /* Enable USBTTL_FCLK */
649 sr32(&prcm_base->fclken3_core, 2, 1, 1);
652 /******************************************************************************
653 * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
654 *****************************************************************************/
655 void per_clocks_enable(void)
657 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
659 /* Enable GP2 timer. */
660 sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
661 sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */
662 sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
664 #ifdef CONFIG_SYS_NS16550
665 /* Enable UART1 clocks */
666 sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
667 sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
670 sr32(&prcm_base->fclken_per, 11, 1, 0x1);
671 sr32(&prcm_base->iclken_per, 11, 1, 0x1);
674 #ifdef CONFIG_OMAP3_GPIO_2
675 sr32(&prcm_base->fclken_per, 13, 1, 1);
676 sr32(&prcm_base->iclken_per, 13, 1, 1);
678 #ifdef CONFIG_OMAP3_GPIO_3
679 sr32(&prcm_base->fclken_per, 14, 1, 1);
680 sr32(&prcm_base->iclken_per, 14, 1, 1);
682 #ifdef CONFIG_OMAP3_GPIO_4
683 sr32(&prcm_base->fclken_per, 15, 1, 1);
684 sr32(&prcm_base->iclken_per, 15, 1, 1);
686 #ifdef CONFIG_OMAP3_GPIO_5
687 sr32(&prcm_base->fclken_per, 16, 1, 1);
688 sr32(&prcm_base->iclken_per, 16, 1, 1);
690 #ifdef CONFIG_OMAP3_GPIO_6
691 sr32(&prcm_base->fclken_per, 17, 1, 1);
692 sr32(&prcm_base->iclken_per, 17, 1, 1);
695 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
696 /* Turn on all 3 I2C clocks */
697 sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
698 sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
700 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
701 sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
703 if (get_cpu_family() != CPU_AM35XX)
704 sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
706 sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
707 sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
708 sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
709 sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
710 sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
711 sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
712 sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
713 if (get_cpu_family() != CPU_AM35XX) {
714 sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
715 sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
717 sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
718 sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);