3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
8 * Derived from Beagle Board and OMAP3 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/arch/clock.h>
31 #include <asm/arch/clocks_omap3.h>
32 #include <asm/arch/mem.h>
33 #include <asm/arch/sys_proto.h>
34 #include <environment.h>
37 /******************************************************************************
38 * get_sys_clk_speed() - determine reference oscillator speed
39 * based on known 32kHz clock and gptimer.
40 *****************************************************************************/
41 u32 get_osc_clk_speed(void)
43 u32 start, cstart, cend, cdiff, cdiv, val;
44 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
45 struct prm *prm_base = (struct prm *)PRM_BASE;
46 struct gptimer *gpt1_base = (struct gptimer *)OMAP34XX_GPT1;
47 struct s32ktimer *s32k_base = (struct s32ktimer *)SYNC_32KTIMER_BASE;
49 val = readl(&prm_base->clksrc_ctrl);
51 if (val & SYSCLKDIV_2)
57 val = readl(&prcm_base->clksel_wkup) | CLKSEL_GPT1;
59 /* select sys_clk for GPT1 */
60 writel(val, &prcm_base->clksel_wkup);
62 /* Enable I and F Clocks for GPT1 */
63 val = readl(&prcm_base->iclken_wkup) | EN_GPT1 | EN_32KSYNC;
64 writel(val, &prcm_base->iclken_wkup);
66 val = readl(&prcm_base->fclken_wkup) | EN_GPT1;
67 writel(val, &prcm_base->fclken_wkup);
69 writel(0, &gpt1_base->tldr); /* start counting at 0 */
70 writel(GPT_EN, &gpt1_base->tclr); /* enable clock */
72 /* enable 32kHz source, determine sys_clk via gauging */
74 /* start time in 20 cycles */
75 start = 20 + readl(&s32k_base->s32k_cr);
77 /* dead loop till start time */
78 while (readl(&s32k_base->s32k_cr) < start);
80 /* get start sys_clk count */
81 cstart = readl(&gpt1_base->tcrr);
83 /* wait for 40 cycles */
84 while (readl(&s32k_base->s32k_cr) < (start + 20)) ;
85 cend = readl(&gpt1_base->tcrr); /* get end sys_clk count */
86 cdiff = cend - cstart; /* get elapsed ticks */
89 /* based on number of ticks assign speed */
92 else if (cdiff > 15200)
94 else if (cdiff > 13000)
96 else if (cdiff > 9000)
98 else if (cdiff > 7600)
104 /******************************************************************************
105 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
106 * input oscillator clock frequency.
107 *****************************************************************************/
108 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
130 * OMAP34XX/35XX specific functions
133 static void dpll3_init_34xx(u32 sil_index, u32 clk_index)
135 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
136 dpll_param *ptr = (dpll_param *) get_core_dpll_param();
137 void (*f_lock_pll) (u32, u32, u32, u32);
138 int xip_safe, p0, p1, p2, p3;
140 xip_safe = is_running_in_sram();
142 /* Moving to the right sysclk and ES rev base */
143 ptr = ptr + (3 * clk_index) + sil_index;
148 * sr32(CM_CLKSEL2_EMU) set override to work when asleep
150 sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
151 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
155 * For OMAP3 ES1.0 Errata 1.50, default value directly doesn't
156 * work. write another value and then default value.
159 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
160 sr32(&prcm_base->clksel1_emu, 16, 5, (CORE_M3X2 + 1)) ;
161 sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
163 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
164 sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
166 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
167 sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
169 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
170 sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
172 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
173 sr32(&prcm_base->clksel1_pll, 6, 1, 0);
176 sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
178 sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
180 sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
182 sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
184 sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
186 sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
187 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
188 sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
190 sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
192 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
194 } else if (is_running_in_flash()) {
196 * if running from flash, jump to small relocated code
199 f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
202 p0 = readl(&prcm_base->clken_pll);
203 sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
204 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
205 sr32(&p0, 4, 4, ptr->fsel);
207 p1 = readl(&prcm_base->clksel1_pll);
208 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
209 sr32(&p1, 27, 5, ptr->m2);
210 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
211 sr32(&p1, 16, 11, ptr->m);
212 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
213 sr32(&p1, 8, 7, ptr->n);
214 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
217 p2 = readl(&prcm_base->clksel_core);
219 sr32(&p2, 8, 4, CORE_SSI_DIV);
221 sr32(&p2, 4, 2, CORE_FUSB_DIV);
223 sr32(&p2, 2, 2, CORE_L4_DIV);
225 sr32(&p2, 0, 2, CORE_L3_DIV);
227 p3 = (u32)&prcm_base->idlest_ckgen;
229 (*f_lock_pll) (p0, p1, p2, p3);
233 static void dpll4_init_34xx(u32 sil_index, u32 clk_index)
235 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
236 dpll_param *ptr = (dpll_param *) get_per_dpll_param();
238 /* Moving it to the right sysclk base */
239 ptr = ptr + clk_index;
241 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
242 sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
243 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
246 * Errata 1.50 Workaround for OMAP3 ES1.0 only
247 * If using default divisors, write default divisor + 1
248 * and then the actual divisor value
251 sr32(&prcm_base->clksel1_emu, 24, 5, (PER_M6X2 + 1));
252 sr32(&prcm_base->clksel1_emu, 24, 5, PER_M6X2);
254 sr32(&prcm_base->clksel_cam, 0, 5, (PER_M5X2 + 1));
255 sr32(&prcm_base->clksel_cam, 0, 5, PER_M5X2);
257 sr32(&prcm_base->clksel_dss, 0, 5, (PER_M4X2 + 1));
258 sr32(&prcm_base->clksel_dss, 0, 5, PER_M4X2);
260 sr32(&prcm_base->clksel_dss, 8, 5, (PER_M3X2 + 1));
261 sr32(&prcm_base->clksel_dss, 8, 5, PER_M3X2);
262 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
263 sr32(&prcm_base->clksel3_pll, 0, 5, (ptr->m2 + 1));
264 sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
267 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */
268 sr32(&prcm_base->clksel2_pll, 8, 11, ptr->m);
270 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
271 sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
273 /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */
274 sr32(&prcm_base->clken_pll, 20, 4, ptr->fsel);
276 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
277 sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
278 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
281 static void dpll5_init_34xx(u32 sil_index, u32 clk_index)
283 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
284 dpll_param *ptr = (dpll_param *) get_per2_dpll_param();
286 /* Moving it to the right sysclk base */
287 ptr = ptr + clk_index;
289 /* PER2 DPLL (DPLL5) */
290 sr32(&prcm_base->clken2_pll, 0, 3, PLL_STOP);
291 wait_on_value(1, 0, &prcm_base->idlest2_ckgen, LDELAY);
292 sr32(&prcm_base->clksel5_pll, 0, 5, ptr->m2); /* set M2 (usbtll_fck) */
293 sr32(&prcm_base->clksel4_pll, 8, 11, ptr->m); /* set m (11-bit multiplier) */
294 sr32(&prcm_base->clksel4_pll, 0, 7, ptr->n); /* set n (7-bit divider)*/
295 sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel); /* FREQSEL */
296 sr32(&prcm_base->clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
297 wait_on_value(1, 1, &prcm_base->idlest2_ckgen, LDELAY);
300 static void mpu_init_34xx(u32 sil_index, u32 clk_index)
302 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
303 dpll_param *ptr = (dpll_param *) get_mpu_dpll_param();
305 /* Moving to the right sysclk and ES rev base */
306 ptr = ptr + (3 * clk_index) + sil_index;
308 /* MPU DPLL (unlocked already) */
310 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
311 sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
313 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
314 sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
316 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
317 sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
319 /* FREQSEL (MPU_DPLL_FREQSEL) : CM_CLKEN_PLL_MPU[4:7] */
320 sr32(&prcm_base->clken_pll_mpu, 4, 4, ptr->fsel);
323 static void iva_init_34xx(u32 sil_index, u32 clk_index)
325 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
326 dpll_param *ptr = (dpll_param *) get_iva_dpll_param();
328 /* Moving to the right sysclk and ES rev base */
329 ptr = ptr + (3 * clk_index) + sil_index;
332 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
333 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
334 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
336 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
337 sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
339 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
340 sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
342 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
343 sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
345 /* FREQSEL (IVA2_DPLL_FREQSEL) : CM_CLKEN_PLL_IVA2[4:7] */
346 sr32(&prcm_base->clken_pll_iva2, 4, 4, ptr->fsel);
348 /* LOCK MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
349 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
351 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
355 * OMAP3630 specific functions
358 static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
360 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
361 dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param();
362 void (*f_lock_pll) (u32, u32, u32, u32);
363 int xip_safe, p0, p1, p2, p3;
365 xip_safe = is_running_in_sram();
367 /* Moving it to the right sysclk base */
373 /* Select relock bypass: CM_CLKEN_PLL[0:2] */
374 sr32(&prcm_base->clken_pll, 0, 3, PLL_FAST_RELOCK_BYPASS);
375 wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen,
378 /* CM_CLKSEL1_EMU[DIV_DPLL3] */
379 sr32(&prcm_base->clksel1_emu, 16, 5, CORE_M3X2);
381 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
382 sr32(&prcm_base->clksel1_pll, 27, 5, ptr->m2);
384 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
385 sr32(&prcm_base->clksel1_pll, 16, 11, ptr->m);
387 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
388 sr32(&prcm_base->clksel1_pll, 8, 7, ptr->n);
390 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
391 sr32(&prcm_base->clksel1_pll, 6, 1, 0);
394 sr32(&prcm_base->clksel_core, 8, 4, CORE_SSI_DIV);
396 sr32(&prcm_base->clksel_core, 4, 2, CORE_FUSB_DIV);
398 sr32(&prcm_base->clksel_core, 2, 2, CORE_L4_DIV);
400 sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
402 sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X);
404 sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
405 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
406 sr32(&prcm_base->clken_pll, 4, 4, ptr->fsel);
408 sr32(&prcm_base->clken_pll, 0, 3, PLL_LOCK);
410 wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen,
412 } else if (is_running_in_flash()) {
414 * if running from flash, jump to small relocated code
417 f_lock_pll = (void *) ((u32) &_end_vect - (u32) &_start +
420 p0 = readl(&prcm_base->clken_pll);
421 sr32(&p0, 0, 3, PLL_FAST_RELOCK_BYPASS);
422 /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
423 sr32(&p0, 4, 4, ptr->fsel);
425 p1 = readl(&prcm_base->clksel1_pll);
426 /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */
427 sr32(&p1, 27, 5, ptr->m2);
428 /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */
429 sr32(&p1, 16, 11, ptr->m);
430 /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */
431 sr32(&p1, 8, 7, ptr->n);
432 /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */
435 p2 = readl(&prcm_base->clksel_core);
437 sr32(&p2, 8, 4, CORE_SSI_DIV);
439 sr32(&p2, 4, 2, CORE_FUSB_DIV);
441 sr32(&p2, 2, 2, CORE_L4_DIV);
443 sr32(&p2, 0, 2, CORE_L3_DIV);
445 p3 = (u32)&prcm_base->idlest_ckgen;
447 (*f_lock_pll) (p0, p1, p2, p3);
451 static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
453 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
454 struct dpll_per_36x_param *ptr;
456 ptr = (struct dpll_per_36x_param *)get_36x_per_dpll_param();
458 /* Moving it to the right sysclk base */
461 /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */
462 sr32(&prcm_base->clken_pll, 16, 3, PLL_STOP);
463 wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY);
465 /* M6 (DIV_DPLL4): CM_CLKSEL1_EMU[24:29] */
466 sr32(&prcm_base->clksel1_emu, 24, 6, ptr->m6);
468 /* M5 (CLKSEL_CAM): CM_CLKSEL1_EMU[0:5] */
469 sr32(&prcm_base->clksel_cam, 0, 6, ptr->m5);
471 /* M4 (CLKSEL_DSS1): CM_CLKSEL_DSS[0:5] */
472 sr32(&prcm_base->clksel_dss, 0, 6, ptr->m4);
474 /* M3 (CLKSEL_DSS1): CM_CLKSEL_DSS[8:13] */
475 sr32(&prcm_base->clksel_dss, 8, 6, ptr->m3);
477 /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */
478 sr32(&prcm_base->clksel3_pll, 0, 5, ptr->m2);
480 /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:19] */
481 sr32(&prcm_base->clksel2_pll, 8, 12, ptr->m);
483 /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */
484 sr32(&prcm_base->clksel2_pll, 0, 7, ptr->n);
486 /* M2DIV (CLKSEL_96M): CM_CLKSEL_CORE[12:13] */
487 sr32(&prcm_base->clksel_core, 12, 2, ptr->m2div);
489 /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */
490 sr32(&prcm_base->clken_pll, 16, 3, PLL_LOCK);
491 wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY);
494 static void mpu_init_36xx(u32 sil_index, u32 clk_index)
496 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
497 dpll_param *ptr = (dpll_param *) get_36x_mpu_dpll_param();
499 /* Moving to the right sysclk */
502 /* MPU DPLL (unlocked already */
504 /* M2 (MPU_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_MPU[0:4] */
505 sr32(&prcm_base->clksel2_pll_mpu, 0, 5, ptr->m2);
507 /* M (MPU_DPLL_MULT) : CM_CLKSEL2_PLL_MPU[8:18] */
508 sr32(&prcm_base->clksel1_pll_mpu, 8, 11, ptr->m);
510 /* N (MPU_DPLL_DIV) : CM_CLKSEL2_PLL_MPU[0:6] */
511 sr32(&prcm_base->clksel1_pll_mpu, 0, 7, ptr->n);
514 static void iva_init_36xx(u32 sil_index, u32 clk_index)
516 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
517 dpll_param *ptr = (dpll_param *)get_36x_iva_dpll_param();
519 /* Moving to the right sysclk */
523 /* EN_IVA2_DPLL : CM_CLKEN_PLL_IVA2[0:2] */
524 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_STOP);
525 wait_on_value(ST_IVA2_CLK, 0, &prcm_base->idlest_pll_iva2, LDELAY);
527 /* M2 (IVA2_DPLL_CLKOUT_DIV) : CM_CLKSEL2_PLL_IVA2[0:4] */
528 sr32(&prcm_base->clksel2_pll_iva2, 0, 5, ptr->m2);
530 /* M (IVA2_DPLL_MULT) : CM_CLKSEL1_PLL_IVA2[8:18] */
531 sr32(&prcm_base->clksel1_pll_iva2, 8, 11, ptr->m);
533 /* N (IVA2_DPLL_DIV) : CM_CLKSEL1_PLL_IVA2[0:6] */
534 sr32(&prcm_base->clksel1_pll_iva2, 0, 7, ptr->n);
536 /* LOCK (MODE (EN_IVA2_DPLL) : CM_CLKEN_PLL_IVA2[0:2] */
537 sr32(&prcm_base->clken_pll_iva2, 0, 3, PLL_LOCK);
539 wait_on_value(ST_IVA2_CLK, 1, &prcm_base->idlest_pll_iva2, LDELAY);
542 /******************************************************************************
543 * prcm_init() - inits clocks for PRCM as defined in clocks.h
544 * called from SRAM, or Flash (using temp SRAM stack).
545 *****************************************************************************/
548 u32 osc_clk = 0, sys_clkin_sel;
549 u32 clk_index, sil_index = 0;
550 struct prm *prm_base = (struct prm *)PRM_BASE;
551 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
554 * Gauge the input clock speed and find out the sys_clkin_sel
555 * value corresponding to the input clock.
557 osc_clk = get_osc_clk_speed();
558 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
560 /* set input crystal speed */
561 sr32(&prm_base->clksel, 0, 3, sys_clkin_sel);
563 /* If the input clock is greater than 19.2M always divide/2 */
564 if (sys_clkin_sel > 2) {
565 /* input clock divider */
566 sr32(&prm_base->clksrc_ctrl, 6, 2, 2);
567 clk_index = sys_clkin_sel / 2;
569 /* input clock divider */
570 sr32(&prm_base->clksrc_ctrl, 6, 2, 1);
571 clk_index = sys_clkin_sel;
574 if (get_cpu_family() == CPU_OMAP36XX) {
576 * In warm reset conditions on OMAP36xx/AM/DM37xx
577 * the rom code incorrectly sets the DPLL4 clock
578 * input divider to /6.5. Section 3.5.3.3.3.2.1 of
579 * the AM/DM37x TRM explains that the /6.5 divider
580 * is used only when the input clock is 13MHz.
582 * If the part is in this cpu family *and* the input
583 * clock *is not* 13 MHz, then reset the DPLL4 clock
584 * input divider to /1 as it should never set to /6.5
587 if (sys_clkin_sel != 1) /* 13 MHz */
588 /* Bit 8: DPLL4_CLKINP_DIV */
589 sr32(&prm_base->clksrc_ctrl, 8, 1, 0);
591 /* Unlock MPU DPLL (slows things down, and needed later) */
592 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
593 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
596 dpll3_init_36xx(0, clk_index);
597 dpll4_init_36xx(0, clk_index);
598 dpll5_init_34xx(0, clk_index);
599 iva_init_36xx(0, clk_index);
600 mpu_init_36xx(0, clk_index);
602 /* Lock MPU DPLL to set frequency */
603 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
604 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
608 * The DPLL tables are defined according to sysclk value and
609 * silicon revision. The clk_index value will be used to get
610 * the values for that input sysclk from the DPLL param table
611 * and sil_index will get the values for that SysClk for the
612 * appropriate silicon rev.
614 if (((get_cpu_family() == CPU_OMAP34XX)
615 && (get_cpu_rev() >= CPU_3XX_ES20)) ||
616 (get_cpu_family() == CPU_AM35XX))
619 /* Unlock MPU DPLL (slows things down, and needed later) */
620 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS);
621 wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu,
624 dpll3_init_34xx(sil_index, clk_index);
625 dpll4_init_34xx(sil_index, clk_index);
626 dpll5_init_34xx(sil_index, clk_index);
627 if (get_cpu_family() != CPU_AM35XX)
628 iva_init_34xx(sil_index, clk_index);
630 mpu_init_34xx(sil_index, clk_index);
632 /* Lock MPU DPLL to set frequency */
633 sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOCK);
634 wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu,
638 /* Set up GPTimers to sys_clk source only */
639 sr32(&prcm_base->clksel_per, 0, 8, 0xff);
640 sr32(&prcm_base->clksel_wkup, 0, 1, 1);
646 * Enable usb ehci uhh, tll clocks
648 void ehci_clocks_enable(void)
650 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
652 /* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */
653 sr32(&prcm_base->iclken_usbhost, 0, 1, 1);
655 * Enable USBHOST_48M_FCLK (USBHOST_FCLK1)
656 * and USBHOST_120M_FCLK (USBHOST_FCLK2)
658 sr32(&prcm_base->fclken_usbhost, 0, 2, 3);
659 /* Enable USBTTL_ICLK */
660 sr32(&prcm_base->iclken3_core, 2, 1, 1);
661 /* Enable USBTTL_FCLK */
662 sr32(&prcm_base->fclken3_core, 2, 1, 1);
665 /******************************************************************************
666 * peripheral_enable() - Enable the clks & power for perifs (GPT2, UART1,...)
667 *****************************************************************************/
668 void per_clocks_enable(void)
670 struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
672 /* Enable GP2 timer. */
673 sr32(&prcm_base->clksel_per, 0, 1, 0x1); /* GPT2 = sys clk */
674 sr32(&prcm_base->iclken_per, 3, 1, 0x1); /* ICKen GPT2 */
675 sr32(&prcm_base->fclken_per, 3, 1, 0x1); /* FCKen GPT2 */
677 #ifdef CONFIG_SYS_NS16550
678 /* Enable UART1 clocks */
679 sr32(&prcm_base->fclken1_core, 13, 1, 0x1);
680 sr32(&prcm_base->iclken1_core, 13, 1, 0x1);
683 sr32(&prcm_base->fclken_per, 11, 1, 0x1);
684 sr32(&prcm_base->iclken_per, 11, 1, 0x1);
687 #ifdef CONFIG_OMAP3_GPIO_2
688 sr32(&prcm_base->fclken_per, 13, 1, 1);
689 sr32(&prcm_base->iclken_per, 13, 1, 1);
691 #ifdef CONFIG_OMAP3_GPIO_3
692 sr32(&prcm_base->fclken_per, 14, 1, 1);
693 sr32(&prcm_base->iclken_per, 14, 1, 1);
695 #ifdef CONFIG_OMAP3_GPIO_4
696 sr32(&prcm_base->fclken_per, 15, 1, 1);
697 sr32(&prcm_base->iclken_per, 15, 1, 1);
699 #ifdef CONFIG_OMAP3_GPIO_5
700 sr32(&prcm_base->fclken_per, 16, 1, 1);
701 sr32(&prcm_base->iclken_per, 16, 1, 1);
703 #ifdef CONFIG_OMAP3_GPIO_6
704 sr32(&prcm_base->fclken_per, 17, 1, 1);
705 sr32(&prcm_base->iclken_per, 17, 1, 1);
708 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
709 /* Turn on all 3 I2C clocks */
710 sr32(&prcm_base->fclken1_core, 15, 3, 0x7);
711 sr32(&prcm_base->iclken1_core, 15, 3, 0x7); /* I2C1,2,3 = on */
713 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
714 sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
716 if (get_cpu_family() != CPU_AM35XX)
717 sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
719 sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
720 sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
721 sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
722 sr32(&prcm_base->fclken_wkup, 0, 32, FCK_WKUP_ON);
723 sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
724 sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
725 sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
726 if (get_cpu_family() != CPU_AM35XX) {
727 sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
728 sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
730 sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
731 sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);