2 * Board specific setup info
5 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Syed Mohammed Khasim <khasim@ti.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/mem.h>
17 #include <asm/arch/clocks_omap3.h>
18 #include <linux/linkage.h>
21 .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
23 #ifdef CONFIG_SPL_BUILD
24 ENTRY(save_boot_params)
25 ldr r4, =omap3_boot_device
30 ENDPROC(save_boot_params)
33 ENTRY(omap3_gp_romcode_call)
34 PUSH {r4-r12, lr} @ Save all registers from ROM code!
35 MOV r12, r0 @ Copy the Service ID in R12
36 MOV r0, r1 @ Copy parameter to R0
37 mcr p15, 0, r0, c7, c10, 4 @ DSB
38 mcr p15, 0, r0, c7, c10, 5 @ DMB
39 .word 0xe1600070 @ SMC #0 to enter monitor - hand assembled
40 @ because we use -march=armv5
42 ENDPROC(omap3_gp_romcode_call)
45 * Funtion for making PPA HAL API calls in secure devices
50 ENTRY(do_omap3_emu_romcode_call)
51 PUSH {r4-r12, lr} @ Save all registers from ROM code!
52 MOV r12, r0 @ Copy the Secure Service ID in R12
53 MOV r3, r1 @ Copy the pointer to va_list in R3
54 MOV r1, #0 @ Process ID - 0
55 MOV r2, #OMAP3_EMU_HAL_START_HAL_CRITICAL @ Copy the pointer
57 MOV r6, #0xFF @ Indicate new Task call
58 mcr p15, 0, r0, c7, c10, 4 @ DSB
59 mcr p15, 0, r0, c7, c10, 5 @ DMB
60 .word 0xe1600071 @ SMC #1 to call PPA service - hand assembled
61 @ because we use -march=armv5
63 ENDPROC(do_omap3_emu_romcode_call)
65 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT)
66 /**************************************************************************
67 * cpy_clk_code: relocates clock code into SRAM where its safer to execute
68 * R1 = SRAM destination address.
69 *************************************************************************/
71 /* Copy DPLL code into SRAM */
72 adr r0, go_to_speed /* copy from start of go_to_speed... */
73 adr r2, lowlevel_init /* ... up to start of low_level_init */
75 ldmia r0!, {r3 - r10} /* copy from source address [r0] */
76 stmia r1!, {r3 - r10} /* copy to target address [r1] */
77 cmp r0, r2 /* until source end address [r2] */
79 mov pc, lr /* back to caller */
82 /* ***************************************************************************
83 * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
84 * -executed from SRAM.
85 * R0 = CM_CLKEN_PLL-bypass value
86 * R1 = CM_CLKSEL1_PLL-m, n, and divider values
87 * R2 = CM_CLKSEL_CORE-divider values
88 * R3 = CM_IDLEST_CKGEN - addr dpll lock wait
90 * Note: If core unlocks/relocks and SDRAM is running fast already it gets
91 * confused. A reset of the controller gets it back. Taking away its
92 * L3 when its not in self refresh seems bad for it. Normally, this
93 * code runs from flash before SDR is init so that should be ok.
94 ****************************************************************************/
98 /* move into fast relock bypass */
102 ldr r5, [r3] /* get status */
103 and r5, r5, #0x1 /* isolate core status */
104 cmp r5, #0x1 /* still locked? */
105 beq wait1 /* if lock, loop */
107 /* set new dpll dividers _after_ in bypass */
109 str r1, [r5] /* set m, n, m2 */
111 str r2, [r5] /* set l3/l4/.. dividers*/
112 ldr r5, pll_div_add3 /* wkup */
113 ldr r2, pll_div_val3 /* rsm val */
115 ldr r5, pll_div_add4 /* gfx */
118 ldr r5, pll_div_add5 /* emu */
122 /* now prepare GPMC (flash) for new dpll speed */
123 /* flash needs to be stable when we jump back to it */
124 ldr r5, flash_cfg3_addr
125 ldr r2, flash_cfg3_val
127 ldr r5, flash_cfg4_addr
128 ldr r2, flash_cfg4_val
130 ldr r5, flash_cfg5_addr
131 ldr r2, flash_cfg5_val
133 ldr r5, flash_cfg1_addr
135 orr r2, r2, #0x3 /* up gpmc divider */
138 /* lock DPLL3 and wait a bit */
139 orr r0, r0, #0x7 /* set up for lock mode */
140 str r0, [r4] /* lock */
141 nop /* ARM slow at this point working at sys_clk */
146 ldr r5, [r3] /* get status */
147 and r5, r5, #0x1 /* isolate core status */
148 cmp r5, #0x1 /* still locked? */
149 bne wait2 /* if lock, loop */
155 mov pc, lr /* back to caller, locked */
158 _go_to_speed: .word go_to_speed
160 /* these constants need to be close for PIC code */
161 /* The Nor has to be in the Flash Base CS0 for this condition to happen */
163 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG1)
165 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG3)
167 .word STNOR_GPMC_CONFIG3
169 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG4)
171 .word STNOR_GPMC_CONFIG4
173 .word STNOR_GPMC_CONFIG5
175 .word (GPMC_CONFIG_CS0_BASE + GPMC_CONFIG5)
185 .word (WKUP_RSM << 1)
199 str ip, [sp] /* stash ip register */
200 mov ip, lr /* save link reg across call */
201 #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
203 * No need to copy/exec the clock code - DPLL adjust already done
204 * in NAND/oneNAND Boot.
206 ldr r1, =SRAM_CLK_CODE
208 #endif /* NAND Boot */
209 mov lr, ip /* restore link reg */
210 ldr ip, [sp] /* restore save ip */
211 /* tail-call s_init to setup pll, mux, memory */
214 ENDPROC(lowlevel_init)
216 /* the literal pools origin */
222 .word LOW_LEVEL_SRAM_STACK
224 /* DPLL(1-4) PARAM TABLES */
227 * Each of the tables has M, N, FREQSEL, M2 values defined for nominal
228 * OPP (1.2V). The fields are defined according to dpll_param struct (clock.c).
229 * The values are defined for all possible sysclk and for ES1 and ES2.
235 .word MPU_M_12_ES1, MPU_N_12_ES1, MPU_FSEL_12_ES1, MPU_M2_12_ES1
237 .word MPU_M_12_ES2, MPU_N_12_ES2, MPU_FSEL_12_ES2, MPU_M2_ES2
239 .word MPU_M_12, MPU_N_12, MPU_FSEL_12, MPU_M2_12
243 .word MPU_M_13_ES1, MPU_N_13_ES1, MPU_FSEL_13_ES1, MPU_M2_13_ES1
245 .word MPU_M_13_ES2, MPU_N_13_ES2, MPU_FSEL_13_ES2, MPU_M2_13_ES2
247 .word MPU_M_13, MPU_N_13, MPU_FSEL_13, MPU_M2_13
251 .word MPU_M_19P2_ES1, MPU_N_19P2_ES1, MPU_FSEL_19P2_ES1, MPU_M2_19P2_ES1
253 .word MPU_M_19P2_ES2, MPU_N_19P2_ES2, MPU_FSEL_19P2_ES2, MPU_M2_19P2_ES2
255 .word MPU_M_19P2, MPU_N_19P2, MPU_FSEL_19P2, MPU_M2_19P2
259 .word MPU_M_26_ES1, MPU_N_26_ES1, MPU_FSEL_26_ES1, MPU_M2_26_ES1
261 .word MPU_M_26_ES2, MPU_N_26_ES2, MPU_FSEL_26_ES2, MPU_M2_26_ES2
263 .word MPU_M_26, MPU_N_26, MPU_FSEL_26, MPU_M2_26
267 .word MPU_M_38P4_ES1, MPU_N_38P4_ES1, MPU_FSEL_38P4_ES1, MPU_M2_38P4_ES1
269 .word MPU_M_38P4_ES2, MPU_N_38P4_ES2, MPU_FSEL_38P4_ES2, MPU_M2_38P4_ES2
271 .word MPU_M_38P4, MPU_N_38P4, MPU_FSEL_38P4, MPU_M2_38P4
274 .globl get_mpu_dpll_param
276 adr r0, mpu_dpll_param
282 .word IVA_M_12_ES1, IVA_N_12_ES1, IVA_FSEL_12_ES1, IVA_M2_12_ES1
284 .word IVA_M_12_ES2, IVA_N_12_ES2, IVA_FSEL_12_ES2, IVA_M2_12_ES2
286 .word IVA_M_12, IVA_N_12, IVA_FSEL_12, IVA_M2_12
290 .word IVA_M_13_ES1, IVA_N_13_ES1, IVA_FSEL_13_ES1, IVA_M2_13_ES1
292 .word IVA_M_13_ES2, IVA_N_13_ES2, IVA_FSEL_13_ES2, IVA_M2_13_ES2
294 .word IVA_M_13, IVA_N_13, IVA_FSEL_13, IVA_M2_13
298 .word IVA_M_19P2_ES1, IVA_N_19P2_ES1, IVA_FSEL_19P2_ES1, IVA_M2_19P2_ES1
300 .word IVA_M_19P2_ES2, IVA_N_19P2_ES2, IVA_FSEL_19P2_ES2, IVA_M2_19P2_ES2
302 .word IVA_M_19P2, IVA_N_19P2, IVA_FSEL_19P2, IVA_M2_19P2
306 .word IVA_M_26_ES1, IVA_N_26_ES1, IVA_FSEL_26_ES1, IVA_M2_26_ES1
308 .word IVA_M_26_ES2, IVA_N_26_ES2, IVA_FSEL_26_ES2, IVA_M2_26_ES2
310 .word IVA_M_26, IVA_N_26, IVA_FSEL_26, IVA_M2_26
314 .word IVA_M_38P4_ES1, IVA_N_38P4_ES1, IVA_FSEL_38P4_ES1, IVA_M2_38P4_ES1
316 .word IVA_M_38P4_ES2, IVA_N_38P4_ES2, IVA_FSEL_38P4_ES2, IVA_M2_38P4_ES2
318 .word IVA_M_38P4, IVA_N_38P4, IVA_FSEL_38P4, IVA_M2_38P4
321 .globl get_iva_dpll_param
323 adr r0, iva_dpll_param
326 /* Core DPLL targets for L3 at 166 & L133 */
330 .word CORE_M_12_ES1, CORE_N_12_ES1, CORE_FSL_12_ES1, CORE_M2_12_ES1
332 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
334 .word CORE_M_12, CORE_N_12, CORE_FSEL_12, CORE_M2_12
338 .word CORE_M_13_ES1, CORE_N_13_ES1, CORE_FSL_13_ES1, CORE_M2_13_ES1
340 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
342 .word CORE_M_13, CORE_N_13, CORE_FSEL_13, CORE_M2_13
346 .word CORE_M_19P2_ES1, CORE_N_19P2_ES1, CORE_FSL_19P2_ES1, CORE_M2_19P2_ES1
348 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
350 .word CORE_M_19P2, CORE_N_19P2, CORE_FSEL_19P2, CORE_M2_19P2
354 .word CORE_M_26_ES1, CORE_N_26_ES1, CORE_FSL_26_ES1, CORE_M2_26_ES1
356 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
358 .word CORE_M_26, CORE_N_26, CORE_FSEL_26, CORE_M2_26
362 .word CORE_M_38P4_ES1, CORE_N_38P4_ES1, CORE_FSL_38P4_ES1, CORE_M2_38P4_ES1
364 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
366 .word CORE_M_38P4, CORE_N_38P4, CORE_FSEL_38P4, CORE_M2_38P4
368 .globl get_core_dpll_param
370 adr r0, core_dpll_param
373 /* PER DPLL values are same for both ES1 and ES2 */
376 .word PER_M_12, PER_N_12, PER_FSEL_12, PER_M2_12
379 .word PER_M_13, PER_N_13, PER_FSEL_13, PER_M2_13
382 .word PER_M_19P2, PER_N_19P2, PER_FSEL_19P2, PER_M2_19P2
385 .word PER_M_26, PER_N_26, PER_FSEL_26, PER_M2_26
388 .word PER_M_38P4, PER_N_38P4, PER_FSEL_38P4, PER_M2_38P4
390 .globl get_per_dpll_param
392 adr r0, per_dpll_param
395 /* PER2 DPLL values */
398 .word PER2_M_12, PER2_N_12, PER2_FSEL_12, PER2_M2_12
401 .word PER2_M_13, PER2_N_13, PER2_FSEL_13, PER2_M2_13
404 .word PER2_M_19P2, PER2_N_19P2, PER2_FSEL_19P2, PER2_M2_19P2
407 .word PER2_M_26, PER2_N_26, PER2_FSEL_26, PER2_M2_26
410 .word PER2_M_38P4, PER2_N_38P4, PER2_FSEL_38P4, PER2_M2_38P4
412 .globl get_per2_dpll_param
414 adr r0, per2_dpll_param
418 * Tables for 36XX/37XX devices
458 /* SYSCLK M N M2 M3 M4 M5 M6 m2DIV */
459 .word 12000, 360, 4, 9, 16, 5, 4, 3, 1
460 .word 13000, 864, 12, 9, 16, 9, 4, 3, 1
461 .word 19200, 360, 7, 9, 16, 5, 4, 3, 1
462 .word 26000, 432, 12, 9, 16, 9, 4, 3, 1
463 .word 38400, 360, 15, 9, 16, 5, 4, 3, 1
467 .word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
469 .word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
471 .word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
473 .word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
475 .word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
478 ENTRY(get_36x_mpu_dpll_param)
479 adr r0, mpu_36x_dpll_param
481 ENDPROC(get_36x_mpu_dpll_param)
483 ENTRY(get_36x_iva_dpll_param)
484 adr r0, iva_36x_dpll_param
486 ENDPROC(get_36x_iva_dpll_param)
488 ENTRY(get_36x_core_dpll_param)
489 adr r0, core_36x_dpll_param
491 ENDPROC(get_36x_core_dpll_param)
493 ENTRY(get_36x_per_dpll_param)
494 adr r0, per_36x_dpll_param
496 ENDPROC(get_36x_per_dpll_param)
498 ENTRY(get_36x_per2_dpll_param)
499 adr r0, per2_36x_dpll_param
501 ENDPROC(get_36x_per2_dpll_param)