2 * Functions related to OMAP3 SDRC.
4 * This file has been created after exctracting and consolidating
5 * the SDRC related content from mem.c and board.c, also created
6 * generic init function (mem_init).
8 * Copyright (C) 2004-2010
9 * Texas Instruments Incorporated - http://www.ti.com/
12 * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
15 * Vaibhav Hiremath <hvaibhav@ti.com>
17 * Original implementation by (mem.c, board.c) :
18 * Sunil Kumar <sunilsaini05@gmail.com>
19 * Shashi Ranjan <shashiranjanmca05@gmail.com>
20 * Manikandan Pillai <mani.pillai@ti.com>
22 * This program is free software; you can redistribute it and/or
23 * modify it under the terms of the GNU General Public License as
24 * published by the Free Software Foundation; either version 2 of
25 * the License, or (at your option) any later version.
27 * This program is distributed in the hope that it will be useful,
28 * but WITHOUT ANY WARRANTY; without even the implied warranty of
29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
30 * GNU General Public License for more details.
32 * You should have received a copy of the GNU General Public License
33 * along with this program; if not, write to the Free Software
34 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
40 #include <asm/arch/mem.h>
41 #include <asm/arch/sys_proto.h>
43 DECLARE_GLOBAL_DATA_PTR;
44 extern omap3_sysinfo sysinfo;
46 static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE;
50 * - Return 1 if mem type in use is SDR
54 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR)
60 * make_cs1_contiguous -
61 * - When we have CS1 populated we want to have it mapped after cs0 to allow
62 * command line mem=xyz use all memory with out discontinuous support
63 * compiled in. We could do it in the ATAG, but there really is two banks...
65 void make_cs1_contiguous(void)
67 u32 size, a_add_low, a_add_high;
69 size = get_sdr_cs_size(CS0);
70 size >>= 25; /* divide by 32 MiB to find size to offset CS1 */
71 a_add_high = (size & 3) << 8; /* set up low field */
72 a_add_low = (size & 0x3C) >> 2; /* set up high field */
73 writel((a_add_high | a_add_low), &sdrc_base->cs_cfg);
80 * - Get size of chip select 0/1
82 u32 get_sdr_cs_size(u32 cs)
86 /* get ram size field */
87 size = readl(&sdrc_base->cs[cs].mcfg) >> 8;
88 size &= 0x3FF; /* remove unwanted bits */
89 size <<= 21; /* multiply by 2 MiB to find size in MB */
95 * - Get offset of cs from cs0 start
97 u32 get_sdr_cs_offset(u32 cs)
104 offset = readl(&sdrc_base->cs_cfg);
105 offset = (offset & 15) << 27 | (offset & 0x30) << 17;
111 * write_sdrc_timings -
112 * - Takes CS and associated timings and initalize SDRAM
113 * - Test CS to make sure it's OK for use
115 static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base,
116 u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr)
118 /* Setup timings we got from the board. */
119 writel(mcfg, &sdrc_base->cs[cs].mcfg);
120 writel(ctrla, &sdrc_actim_base->ctrla);
121 writel(ctrlb, &sdrc_actim_base->ctrlb);
122 writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl);
123 writel(CMD_NOP, &sdrc_base->cs[cs].manual);
124 writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual);
125 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
126 writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual);
127 writel(mr, &sdrc_base->cs[cs].mr);
130 * Test ram in this bank
131 * Disable if bad or not present
134 writel(0, &sdrc_base->cs[cs].mcfg);
139 * - Code called once in C-Stack only context for CS0 and with early being
140 * true and a possible 2nd time depending on memory configuration from
141 * stack+global context.
143 void do_sdrc_init(u32 cs, u32 early)
145 struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1;
146 u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr;
148 sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE;
149 sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
152 * When called in the early context this may be SPL and we will
153 * need to set all of the timings. This ends up being board
154 * specific so we call a helper function to take care of this
155 * for us. Otherwise, to be safe, we need to copy the settings
156 * from the first bank to the second. We will setup CS0,
157 * then set cs_cfg to the appropriate value then try and
160 #ifdef CONFIG_SPL_BUILD
161 get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr);
164 /* reset sdrc controller */
165 writel(SOFTRESET, &sdrc_base->sysconfig);
166 wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status,
168 writel(0, &sdrc_base->sysconfig);
170 /* setup sdrc to ball mux */
171 writel(SDRC_SHARING, &sdrc_base->sharing);
173 /* Disable Power Down of CKE because of 1 CKE on combo part */
174 writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH,
177 writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl);
179 #ifdef CONFIG_SPL_BUILD
180 write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb,
182 make_cs1_contiguous();
183 write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb,
190 * If we aren't using SPL we have been loaded by some
191 * other means which may not have correctly initialized
192 * both CS0 and CS1 (such as some older versions of x-loader)
193 * so we may be asked now to setup CS1.
196 mcfg = readl(&sdrc_base->cs[CS0].mcfg),
197 rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl);
198 ctrla = readl(&sdrc_actim_base0->ctrla),
199 ctrlb = readl(&sdrc_actim_base0->ctrlb);
200 mr = readl(&sdrc_base->cs[CS0].mr);
201 write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb,
209 * - Sets uboots idea of sdram size
213 unsigned int size0 = 0, size1 = 0;
215 size0 = get_sdr_cs_size(CS0);
217 * We always need to have cs_cfg point at where the second
218 * bank would be, if present. Failure to do so can lead to
219 * strange situations where memory isn't detected and
220 * configured correctly. CS0 will already have been setup
223 make_cs1_contiguous();
224 do_sdrc_init(CS1, NOT_EARLY);
225 size1 = get_sdr_cs_size(CS1);
227 gd->ram_size = size0 + size1;
232 void dram_init_banksize (void)
234 unsigned int size0 = 0, size1 = 0;
236 size0 = get_sdr_cs_size(CS0);
237 size1 = get_sdr_cs_size(CS1);
239 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
240 gd->bd->bi_dram[0].size = size0;
241 gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
242 gd->bd->bi_dram[1].size = size1;
247 * - Init the sdrc chip,
248 * - Selects CS0 and CS1,
252 /* only init up first bank here */
253 do_sdrc_init(CS0, EARLY_INIT);