2 * Copyright (C) 2009 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
4 * Heungjun Kim <riverful.kim@samsung.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/arch/clock.h>
28 #include <asm/arch/clk.h>
34 #ifndef CONFIG_SYS_CLK_FREQ_C100
35 #define CONFIG_SYS_CLK_FREQ_C100 12000000
37 #ifndef CONFIG_SYS_CLK_FREQ_C110
38 #define CONFIG_SYS_CLK_FREQ_C110 24000000
41 unsigned long (*get_pclk)(void);
42 unsigned long (*get_arm_clk)(void);
43 unsigned long (*get_pll_clk)(int);
45 /* s5pc110: return pll clock frequency */
46 static unsigned long s5pc100_get_pll_clk(int pllreg)
48 struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
49 unsigned long r, m, p, s, mask, fout;
54 r = readl(&clk->apll_con);
57 r = readl(&clk->mpll_con);
60 r = readl(&clk->epll_con);
63 r = readl(&clk->hpll_con);
66 printf("Unsupported PLL (%d)\n", pllreg);
71 * APLL_CON: MIDV [25:16]
72 * MPLL_CON: MIDV [23:16]
73 * EPLL_CON: MIDV [23:16]
74 * HPLL_CON: MIDV [23:16]
88 /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
89 freq = CONFIG_SYS_CLK_FREQ_C100;
90 fout = m * (freq / (p * (1 << s)));
95 /* s5pc100: return pll clock frequency */
96 static unsigned long s5pc110_get_pll_clk(int pllreg)
98 struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
99 unsigned long r, m, p, s, mask, fout;
104 r = readl(&clk->apll_con);
107 r = readl(&clk->mpll_con);
110 r = readl(&clk->epll_con);
113 r = readl(&clk->vpll_con);
116 printf("Unsupported PLL (%d)\n", pllreg);
121 * APLL_CON: MIDV [25:16]
122 * MPLL_CON: MIDV [25:16]
123 * EPLL_CON: MIDV [24:16]
124 * VPLL_CON: MIDV [24:16]
126 if (pllreg == APLL || pllreg == MPLL)
131 m = (r >> 16) & mask;
138 freq = CONFIG_SYS_CLK_FREQ_C110;
139 if (pllreg == APLL) {
142 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
143 fout = m * (freq / (p * (1 << (s - 1))));
145 /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
146 fout = m * (freq / (p * (1 << s)));
151 /* s5pc110: return ARM clock frequency */
152 static unsigned long s5pc110_get_arm_clk(void)
154 struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
156 unsigned long dout_apll, armclk;
157 unsigned int apll_ratio;
159 div = readl(&clk->div0);
161 /* APLL_RATIO: [2:0] */
162 apll_ratio = div & 0x7;
164 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
170 /* s5pc100: return ARM clock frequency */
171 static unsigned long s5pc100_get_arm_clk(void)
173 struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
175 unsigned long dout_apll, armclk;
176 unsigned int apll_ratio, arm_ratio;
178 div = readl(&clk->div0);
180 /* ARM_RATIO: [6:4] */
181 arm_ratio = (div >> 4) & 0x7;
182 /* APLL_RATIO: [0] */
183 apll_ratio = div & 0x1;
185 dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
186 armclk = dout_apll / (arm_ratio + 1);
191 /* s5pc100: return HCLKD0 frequency */
192 static unsigned long get_hclk(void)
194 struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
195 unsigned long hclkd0;
196 uint div, d0_bus_ratio;
198 div = readl(&clk->div0);
199 /* D0_BUS_RATIO: [10:8] */
200 d0_bus_ratio = (div >> 8) & 0x7;
202 hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
207 /* s5pc100: return PCLKD1 frequency */
208 static unsigned long get_pclkd1(void)
210 struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
211 unsigned long d1_bus, pclkd1;
212 uint div, d1_bus_ratio, pclkd1_ratio;
214 div = readl(&clk->div0);
215 /* D1_BUS_RATIO: [14:12] */
216 d1_bus_ratio = (div >> 12) & 0x7;
217 /* PCLKD1_RATIO: [18:16] */
218 pclkd1_ratio = (div >> 16) & 0x7;
221 d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
222 pclkd1 = d1_bus / (pclkd1_ratio + 1);
227 /* s5pc110: return HCLKs frequency */
228 static unsigned long get_hclk_sys(int dom)
230 struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
234 unsigned int hclk_sys_ratio;
239 div = readl(&clk->div0);
242 * HCLK_MSYS_RATIO: [10:8]
243 * HCLK_DSYS_RATIO: [19:16]
244 * HCLK_PSYS_RATIO: [27:24]
246 offset = 8 + (dom << 0x3);
248 hclk_sys_ratio = (div >> offset) & 0xf;
250 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
255 /* s5pc110: return PCLKs frequency */
256 static unsigned long get_pclk_sys(int dom)
258 struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
262 unsigned int pclk_sys_ratio;
264 div = readl(&clk->div0);
267 * PCLK_MSYS_RATIO: [14:12]
268 * PCLK_DSYS_RATIO: [22:20]
269 * PCLK_PSYS_RATIO: [30:28]
271 offset = 12 + (dom << 0x3);
273 pclk_sys_ratio = (div >> offset) & 0x7;
275 pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
280 /* s5pc110: return peripheral clock frequency */
281 static unsigned long s5pc110_get_pclk(void)
283 return get_pclk_sys(CLK_P);
286 /* s5pc100: return peripheral clock frequency */
287 static unsigned long s5pc100_get_pclk(void)
292 void s5pc1xx_clock_init(void)
294 if (cpu_is_s5pc110()) {
295 get_pll_clk = s5pc110_get_pll_clk;
296 get_arm_clk = s5pc110_get_arm_clk;
297 get_pclk = s5pc110_get_pclk;
299 get_pll_clk = s5pc100_get_pll_clk;
300 get_arm_clk = s5pc100_get_arm_clk;
301 get_pclk = s5pc100_get_pclk;