2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock_manager.h>
11 static const struct socfpga_clock_manager *clock_manager_base =
12 (void *)SOCFPGA_CLKMGR_ADDRESS;
14 #define CLKMGR_BYPASS_ENABLE 1
15 #define CLKMGR_BYPASS_DISABLE 0
16 #define CLKMGR_STAT_IDLE 0
17 #define CLKMGR_STAT_BUSY 1
18 #define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
19 #define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
20 #define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
21 #define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
23 #define CLEAR_BGP_EN_PWRDN \
24 (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
25 CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
26 CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
29 (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
30 CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
31 CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
33 static void cm_wait_for_lock(uint32_t mask)
35 register uint32_t inter_val;
37 inter_val = readl(&clock_manager_base->inter) & mask;
38 } while (inter_val != mask);
41 /* function to poll in the fsm busy bit */
42 static void cm_wait_for_fsm(void)
44 while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
49 * function to write the bypass register which requires a poll of the
52 static void cm_write_bypass(uint32_t val)
54 writel(val, &clock_manager_base->bypass);
58 /* function to write the ctrl register which requires a poll of the busy bit */
59 static void cm_write_ctrl(uint32_t val)
61 writel(val, &clock_manager_base->ctrl);
65 /* function to write a clock register that has phase information */
66 static void cm_write_with_phase(uint32_t value,
67 uint32_t reg_address, uint32_t mask)
69 /* poll until phase is zero */
70 while (readl(reg_address) & mask)
73 writel(value, reg_address);
75 while (readl(reg_address) & mask)
80 * Setup clocks while making no assumptions about previous state of the clocks.
82 * Start by being paranoid and gate all sw managed clocks
83 * Put all plls in bypass
84 * Put all plls VCO registers back to reset value (bandgap power down).
85 * Put peripheral and main pll src to reset value to avoid glitch.
87 * Deassert bandgap power down and set numerator and denominator
89 * set internal dividers
90 * Wait for 7 us timer.
92 * Set external dividers while plls are locking
94 * Assert/deassert outreset all.
95 * Take all pll's out of bypass
97 * set source main and peripheral clocks
101 void cm_basic_init(const cm_config_t *cfg)
103 uint32_t start, timeout;
105 /* Start by being paranoid and gate all sw managed clocks */
108 * We need to disable nandclk
109 * and then do another apb access before disabling
110 * gatting off the rest of the periperal clocks.
112 writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
113 readl(&clock_manager_base->per_pll.en),
114 &clock_manager_base->per_pll.en);
116 /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
117 writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
118 CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
119 CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
120 CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
121 CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
122 CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
123 &clock_manager_base->main_pll.en);
125 writel(0, &clock_manager_base->sdr_pll.en);
127 /* now we can gate off the rest of the peripheral clocks */
128 writel(0, &clock_manager_base->per_pll.en);
130 /* Put all plls in bypass */
132 CLKMGR_BYPASS_PERPLLSRC_SET(
133 CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
134 CLKMGR_BYPASS_SDRPLLSRC_SET(
135 CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
136 CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
137 CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
138 CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
141 * Put all plls VCO registers back to reset value.
142 * Some code might have messed with them.
144 writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
145 &clock_manager_base->main_pll.vco);
146 writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
147 &clock_manager_base->per_pll.vco);
148 writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
149 &clock_manager_base->sdr_pll.vco);
152 * The clocks to the flash devices and the L4_MAIN clocks can
153 * glitch when coming out of safe mode if their source values
154 * are different from their reset value. So the trick it to
155 * put them back to their reset state, and change input
156 * after exiting safe mode but before ungating the clocks.
158 writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
159 &clock_manager_base->per_pll.src);
160 writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
161 &clock_manager_base->main_pll.l4src);
163 /* read back for the required 5 us delay. */
164 readl(&clock_manager_base->main_pll.vco);
165 readl(&clock_manager_base->per_pll.vco);
166 readl(&clock_manager_base->sdr_pll.vco);
170 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
171 * with numerator and denominator.
173 writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
174 CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
175 &clock_manager_base->main_pll.vco);
177 writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
178 CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
179 &clock_manager_base->per_pll.vco);
181 writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
182 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
183 cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
184 CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
185 &clock_manager_base->sdr_pll.vco);
189 * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
191 start = get_timer(0);
192 /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
196 writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
198 /* main main clock */
199 writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
202 writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
204 /* main for cfgs2fuser0clk */
205 writel(cfg->cfg2fuser0clk,
206 &clock_manager_base->main_pll.cfgs2fuser0clk);
208 /* Peri emac0 50 MHz default to RMII */
209 writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
211 /* Peri emac1 50 MHz default to RMII */
212 writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
215 writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
217 writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
219 /* Peri pernandsdmmcclk */
220 writel(cfg->pernandsdmmcclk,
221 &clock_manager_base->per_pll.pernandsdmmcclk);
223 /* Peri perbaseclk */
224 writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
226 /* Peri s2fuser1clk */
227 writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
229 /* 7 us must have elapsed before we can enable the VCO */
230 while (get_timer(start) < timeout)
235 writel(cfg->main_vco_base | VCO_EN_BASE,
236 &clock_manager_base->main_pll.vco);
239 writel(cfg->peri_vco_base | VCO_EN_BASE,
240 &clock_manager_base->per_pll.vco);
243 writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
244 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
245 cfg->sdram_vco_base | VCO_EN_BASE,
246 &clock_manager_base->sdr_pll.vco);
248 /* L3 MP and L3 SP */
249 writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
251 writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
253 writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
255 /* L4 MP, L4 SP, can0, and can1 */
256 writel(cfg->perdiv, &clock_manager_base->per_pll.div);
258 writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
260 #define LOCKED_MASK \
261 (CLKMGR_INTER_SDRPLLLOCKED_MASK | \
262 CLKMGR_INTER_PERPLLLOCKED_MASK | \
263 CLKMGR_INTER_MAINPLLLOCKED_MASK)
265 cm_wait_for_lock(LOCKED_MASK);
267 /* write the sdram clock counters before toggling outreset all */
268 writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
269 &clock_manager_base->sdr_pll.ddrdqsclk);
271 writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
272 &clock_manager_base->sdr_pll.ddr2xdqsclk);
274 writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
275 &clock_manager_base->sdr_pll.ddrdqclk);
277 writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
278 &clock_manager_base->sdr_pll.s2fuser2clk);
281 * after locking, but before taking out of bypass
282 * assert/deassert outresetall
284 uint32_t mainvco = readl(&clock_manager_base->main_pll.vco);
286 /* assert main outresetall */
287 writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
288 &clock_manager_base->main_pll.vco);
290 uint32_t periphvco = readl(&clock_manager_base->per_pll.vco);
292 /* assert pheriph outresetall */
293 writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
294 &clock_manager_base->per_pll.vco);
296 /* assert sdram outresetall */
297 writel(cfg->sdram_vco_base | VCO_EN_BASE|
298 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
299 &clock_manager_base->sdr_pll.vco);
301 /* deassert main outresetall */
302 writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
303 &clock_manager_base->main_pll.vco);
305 /* deassert pheriph outresetall */
306 writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
307 &clock_manager_base->per_pll.vco);
309 /* deassert sdram outresetall */
310 writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
311 cfg->sdram_vco_base | VCO_EN_BASE,
312 &clock_manager_base->sdr_pll.vco);
315 * now that we've toggled outreset all, all the clocks
316 * are aligned nicely; so we can change any phase.
318 cm_write_with_phase(cfg->ddrdqsclk,
319 (uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk,
320 CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
322 /* SDRAM DDR2XDQSCLK */
323 cm_write_with_phase(cfg->ddr2xdqsclk,
324 (uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk,
325 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
327 cm_write_with_phase(cfg->ddrdqclk,
328 (uint32_t)&clock_manager_base->sdr_pll.ddrdqclk,
329 CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
331 cm_write_with_phase(cfg->s2fuser2clk,
332 (uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk,
333 CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
335 /* Take all three PLLs out of bypass when safe mode is cleared. */
337 CLKMGR_BYPASS_PERPLLSRC_SET(
338 CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
339 CLKMGR_BYPASS_SDRPLLSRC_SET(
340 CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
341 CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
342 CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
343 CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
345 /* clear safe mode */
346 cm_write_ctrl(readl(&clock_manager_base->ctrl) |
347 CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
350 * now that safe mode is clear with clocks gated
351 * it safe to change the source mux for the flashes the the L4_MAIN
353 writel(cfg->persrc, &clock_manager_base->per_pll.src);
354 writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
356 /* Now ungate non-hw-managed clocks */
357 writel(~0, &clock_manager_base->main_pll.en);
358 writel(~0, &clock_manager_base->per_pll.en);
359 writel(~0, &clock_manager_base->sdr_pll.en);