2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/reset_manager.h>
12 #include <asm/arch/system_manager.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 static struct socfpga_system_manager *sysmgr_regs =
17 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
21 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
26 * DesignWare Ethernet initialization
28 #ifdef CONFIG_DESIGNWARE_ETH
29 int cpu_eth_init(bd_t *bis)
31 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
32 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
33 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
34 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
36 #error "Incorrect CONFIG_EMAC_BASE value!"
39 /* Initialize EMAC. This needs to be done at least once per boot. */
42 * Putting the EMAC controller to reset when configuring the PHY
43 * interface select at System Manager
45 socfpga_emac_reset(1);
47 /* Clearing emac0 PHY interface select to 0 */
48 clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
49 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
51 /* configure to PHY interface select choosed */
52 setbits_le32(&sysmgr_regs->emacgrp_ctrl,
53 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
55 /* Release the EMAC controller from reset */
56 socfpga_emac_reset(0);
58 /* initialize and register the emac */
59 return designware_initialize(CONFIG_EMAC_BASE,
60 CONFIG_PHY_INTERFACE_MODE);
64 #if defined(CONFIG_DISPLAY_CPUINFO)
66 * Print CPU information
68 int print_cpuinfo(void)
70 puts("CPU : Altera SOCFPGA Platform\n");
75 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
76 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
77 int overwrite_console(void)
83 int arch_cpu_init(void)
86 * If the HW watchdog is NOT enabled, make sure it is not running,
87 * for example because it was enabled in the preloader. This might
88 * trigger a watchdog-triggered reboot of Linux kernel later.
90 #ifndef CONFIG_HW_WATCHDOG
91 socfpga_watchdog_reset();